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1.发明申请Electron induced chemical etching/deposition for enhanced detection of surface defects 有权电子诱导化学蚀刻/沉积，以增强表面缺陷的检测公开(公告)号：US20080006786A1
公开(公告)日：2008-01-10
申请号：US11483800
申请日：2006-07-10
申请人： Mark J. Williamson , Paul M. Johnson , Shawn D. Lyonsmith , Gurtej S. Sandhu , Justin R. Arrington
发明人： Mark J. Williamson , Paul M. Johnson , Shawn D. Lyonsmith , Gurtej S. Sandhu , Justin R. Arrington
CPC分类号： G01N1/32
摘要： A method of imaging and identifying defects and contamination on the surface of an integrated circuit is described. The method may be used on areas smaller than one micron in diameter. An energetic beam, such as an electron beam, is directed at a selected IC location having a layer of a solid, fluid or gaseous reactive material formed over the surface. The energetic beam disassociates the reactive material in the region into chemical radicals that either chemically etch the surface preferentially, or deposit a thin layer of a conductive material over the local area around the energetic beam. The surface may be examined as various layers are selectively etched to decorate defects and/or as various layers are locally deposited in the area around the energetic beam. SEM imaging and other analytic methods may be used to identify the problem more easily.
摘要翻译： 描述了在集成电路的表面上成像和识别缺陷和污染的方法。 该方法可以用于直径小于1微米的区域。 诸如电子束的能量束被引导到选定的IC位置，其具有形成在表面上的固体，流体或气态反应性材料层。 能量束将该区域中的反应性材料分解成化学自由基，其优先化学蚀刻表面，或者在能量束周围的局部区域上沉积导电材料的薄层。 可以检查表面，因为选择性地蚀刻各种层以修饰缺陷和/或当各种层局部沉积在能量束周围的区域中时。 可以使用SEM成像和其他分析方法来更容易地识别问题。
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2.发明申请METHOD OF REDUCING DAMAGE TO AN ELECTRON BEAM INSPECTED SEMICONDUCTOR SUBSTRATE, AND METHODS OF INSPECTING A SEMICONDUCTOR SUBSTRATE 有权减少对电子束检测半导体基板的损害的方法以及检查半导体基板的方法公开(公告)号：US20130011940A1
公开(公告)日：2013-01-10
申请号：US13615155
申请日：2012-09-13
IPC分类号： H01L21/66
CPC分类号： H01L21/02074
摘要： Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.
摘要翻译： 减少电子束对半导体衬底的损伤的方法采用诸如小链有机溶剂和非中性pH溶液的组合物来减少或消除由半导体衬底的电子束检查引起的半导体衬底上的电荷失衡。 通过电子束检查过程对半导体衬底的损伤也可以通过在电子束检查之后在半导体衬底上产生或以其他方式形成钝化膜来降低。
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3.发明授权Method of removing or deposting material on a surface including material selected to decorate a particle on the surface for imaging 有权在包括选择用于装饰表面上的颗粒以进行成像的材料的表面上去除或沉积材料的方法公开(公告)号：US08026501B2
公开(公告)日：2011-09-27
申请号：US12869538
申请日：2010-08-26
申请人： Mark J. Williamson , Paul M. Johnson , Shawn D. Lyonsmith , Gurtej S. Sandhu , Justin R. Arrington
发明人： Mark J. Williamson , Paul M. Johnson , Shawn D. Lyonsmith , Gurtej S. Sandhu , Justin R. Arrington
IPC分类号： G01N21/86
CPC分类号： G01N1/32
摘要： A method that may be applied to imaging and identifying defects and contamination on the surface of an integrated circuit is described. An energetic beam, such as an electron beam, may be directed at a selected IC location having a layer of a solid, fluid, or gaseous reactive material formed over the surface. The energetic beam disassociates the reactive material in the region into chemical radicals that either chemically etch the surface preferentially, or deposit a thin layer of a conductive material over the local area around the energetic beam. The surface may be examined as various layers are selectively etched to decorate defects and/or as various layers are locally deposited in the area around the energetic beam. SEM imaging and other analytic methods may be used to identify the problem more easily.
摘要翻译： 描述了可应用于成像和识别集成电路表面上的缺陷和污染的方法。 诸如电子束的能量束可以被引导到具有在表面上形成的固体，流体或气态反应性材料层的选定IC位置。 能量束将该区域中的反应性材料分解成化学自由基，其优先化学蚀刻表面，或者在能量束周围的局部区域上沉积导电材料的薄层。 可以检查表面，因为选择性地蚀刻各种层以修饰缺陷和/或当各种层局部沉积在能量束周围的区域中时。 可以使用SEM成像和其他分析方法来更容易地识别问题。
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公开(公告)号：US20100320384A1
公开(公告)日：2010-12-23
申请号：US12869538
申请日：2010-08-26
申请人： Mark J. Williamson , Paul M. Johnson , Shawn D. Lyonsmith , Gurtel S. Sandhu , Justin R. Arrington
发明人： Mark J. Williamson , Paul M. Johnson , Shawn D. Lyonsmith , Gurtel S. Sandhu , Justin R. Arrington
CPC分类号： G01N1/32
摘要： A method that may be applied to imaging and identifying defects and contamination on the surface of an integrated circuit is described. An energetic beam, such as an electron beam, may be directed at a selected IC location having a layer of a solid, fluid, or gaseous reactive material formed over the surface. The energetic beam disassociates the reactive material in the region into chemical radicals that either chemically etch the surface preferentially, or deposit a thin layer of a conductive material over the local area around the energetic beam. The surface may be examined as various layers are selectively etched to decorate defects and/or as various layers are locally deposited in the area around the energetic beam. SEM imaging and other analytic methods may be used to identify the problem more easily.
摘要翻译： 描述了可应用于成像和识别集成电路表面上的缺陷和污染的方法。 诸如电子束的能量束可以被引导到具有在表面上形成的固体，流体或气态反应性材料层的选定IC位置。 能量束将该区域中的反应性材料分解成化学自由基，其优先化学蚀刻表面，或者在能量束周围的局部区域上沉积导电材料的薄层。 可以检查表面，因为选择性地蚀刻各种层以修饰缺陷和/或当各种层局部沉积在能量束周围的区域中时。 可以使用SEM成像和其他分析方法来更容易地识别问题。
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公开(公告)号：US20080076263A1
公开(公告)日：2008-03-27
申请号：US11525492
申请日：2006-09-21
IPC分类号： H01L21/31
CPC分类号： H01L21/02074
摘要： Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.
摘要翻译： 减少电子束对半导体衬底的损伤的方法采用诸如小链有机溶剂和非中性pH溶液的组合物来减少或消除由半导体衬底的电子束检查引起的半导体衬底上的电荷失衡。 通过电子束检查过程对半导体衬底的损伤也可以通过在电子束检查之后通过在半导体衬底上产生或以其它方式形成钝化膜来降低。
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6.发明授权Method of reducing damage to an electron beam inspected semiconductor substrate, and methods of inspecting a semiconductor substrate 有权减少对电子束检查的半导体衬底的损伤的方法，以及检查半导体衬底的方法公开(公告)号：US08563435B2
公开(公告)日：2013-10-22
申请号：US13615155
申请日：2012-09-13
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/02074
摘要： Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.
摘要翻译： 减少电子束对半导体衬底的损伤的方法采用诸如小链有机溶剂和非中性pH溶液的组合物来减少或消除由半导体衬底的电子束检查引起的半导体衬底上的电荷失衡。 通过电子束检查过程对半导体衬底的损伤也可以通过在电子束检查之后在半导体衬底上产生或以其他方式形成钝化膜来降低。
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公开(公告)号：US08334209B2
公开(公告)日：2012-12-18
申请号：US11525492
申请日：2006-09-21
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/02074
摘要： Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.
摘要翻译： 减少电子束对半导体衬底的损伤的方法采用诸如小链有机溶剂和非中性pH溶液的组合物来减少或消除由半导体衬底的电子束检查引起的半导体衬底上的电荷失衡。 通过电子束检查过程对半导体衬底的损伤也可以通过在电子束检查之后在半导体衬底上产生或以其他方式形成钝化膜来降低。
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8.发明授权Electron induced chemical etching/deposition for enhanced detection of surface defects 有权电子诱导化学蚀刻/沉积，以增强表面缺陷的检测公开(公告)号：US07791055B2
公开(公告)日：2010-09-07
申请号：US11483800
申请日：2006-07-10
申请人： Mark J. Williamson , Paul M. Johnson , Shawn D. Lyonsmith , Gurtej S. Sandhu , Justin R. Arrington
发明人： Mark J. Williamson , Paul M. Johnson , Shawn D. Lyonsmith , Gurtej S. Sandhu , Justin R. Arrington
IPC分类号： G01N21/86
CPC分类号： G01N1/32
摘要： A method of imaging and identifying defects and contamination on the surface of an integrated circuit is described. The method may be used on areas smaller than one micron in diameter. An energetic beam, such as an electron beam, is directed at a selected IC location having a layer of a solid, fluid or gaseous reactive material formed over the surface. The energetic beam disassociates the reactive material in the region into chemical radicals that either chemically etch the surface preferentially, or deposit a thin layer of a conductive material over the local area around the energetic beam. The surface may be examined as various layers are selectively etched to decorate defects and/or as various layers are locally deposited in the area around the energetic beam. SEM imaging and other analytic methods may be used to identify the problem more easily.
摘要翻译： 描述了在集成电路的表面上成像和识别缺陷和污染的方法。 该方法可以用于直径小于1微米的区域。 诸如电子束的能量束被引导到选定的IC位置，其具有形成在表面上的固体，流体或气态反应性材料层。 能量束将该区域中的反应性材料分解成化学自由基，其优先化学蚀刻表面，或者在能量束周围的局部区域上沉积导电材料的薄层。 可以检查表面，因为选择性地蚀刻各种层以修饰缺陷和/或当各种层局部沉积在能量束周围的区域中时。 可以使用SEM成像和其他分析方法来更容易地识别问题。
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9.发明授权Biasable isolation regions using epitaxially grown silicon between the isolation regions 有权在隔离区域之间使用外延生长的硅的可偏置隔离区公开(公告)号：US06919612B2
公开(公告)日：2005-07-19
申请号：US10447808
申请日：2003-05-29
IPC分类号： H01L21/20 , H01L21/762 , H01L21/763 , H01L29/00
CPC分类号： H01L21/762 , H01L21/02381 , H01L21/02392 , H01L21/02395 , H01L21/02532 , H01L21/0262 , H01L21/763
摘要： An improved isolation structure for use in an integrated circuit and a method for making the same is disclosed. In a preferred embodiment, an silicon dioxide, polysilicon, silicon dioxide stack is formed on a crystalline silicon substrate. The active areas are etched to expose the substrate, and sidewall oxides are formed on the resulting stacks to define the isolation structures, which in a preferred embodiment constitute dielectric boxes containing the polysilicon in their centers. Epitaxial silicon is grown on the exposed areas of substrate so that it is substantially as thick as the isolation structure, and these grown areas define the active areas of the substrate upon which electrical structures such as transistors can be formed. While the dielectric box provides isolation, further isolation can be provided by placing a contact to the polysilicon within the box and by providing a bias voltage to the polysilicon.
摘要翻译： 公开了用于集成电路的改进的隔离结构及其制造方法。 在优选实施例中，在晶体硅衬底上形成二氧化硅，多晶硅，二氧化硅堆叠。 蚀刻有源区域以露出衬底，并且在所得到的叠层上形成侧壁氧化物以限定隔离结构，其在优选实施例中构成在其中心中包含多晶硅的电介质盒。 外延硅在衬底的暴露区域上生长，使得其基本上与隔离结构一样厚，并且这些生长区域限定衬底的有源区域，在其上可以形成诸如晶体管的电结构。 虽然电介质盒提供隔离，但是可以通过将接触放置在盒内的多晶硅并通过向多晶硅提供偏置电压来提供进一步的隔离。
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10.发明授权Method of forming biasable isolation regions using epitaxially grown silicon between the isolation regions 有权在隔离区域之间使用外延生长的硅形成可偏置隔离区的方法公开(公告)号：US06716719B2
公开(公告)日：2004-04-06
申请号：US10157049
申请日：2002-05-29
IPC分类号： H01L2176
CPC分类号： H01L21/762 , H01L21/02381 , H01L21/02392 , H01L21/02395 , H01L21/02532 , H01L21/0262 , H01L21/763
摘要： An improved isolation structure for use in an integrated circuit and a method for making the same is disclosed. In a preferred embodiment, an silicon dioxide, polysilicon, silicon dioxide stack is formed on a crystalline silicon substrate. The active areas are etched to expose the substrate, and sidewall oxides are formed on the resulting stacks to define the isolation structures, which in a preferred embodiment constitute dielectric boxes containing the polysilicon in their centers. Epitaxial silicon is grown on the exposed areas of substrate so that it is substantially as thick as the isolation structure, and these grown areas define the active areas of the substrate upon which electrical structures such as transistors can be formed. While the dielectric box provides isolation, further isolation can be provided by placing a contact to the polysilicon within the box and by providing a bias voltage to the polysilicon.
摘要翻译： 公开了用于集成电路的改进的隔离结构及其制造方法。 在优选实施例中，在晶体硅衬底上形成二氧化硅，多晶硅，二氧化硅堆叠。 蚀刻有源区域以露出衬底，并且在所得到的叠层上形成侧壁氧化物以限定隔离结构，其在优选实施例中构成在其中心中包含多晶硅的电介质盒。 外延硅在衬底的暴露区域上生长，使得其基本上与隔离结构一样厚，并且这些生长区域限定衬底的有源区域，在其上可以形成诸如晶体管的电结构。 虽然电介质盒提供隔离，但是可以通过将接触放置在盒内的多晶硅并通过向多晶硅提供偏置电压来提供进一步的隔离。
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