公开(公告)号：US4984190A

公开(公告)日：1991-01-08

申请号：US569539

申请日：1990-08-20

申请人： Shigetatsu Katori ,  Yukio Maehashi ,  Yukari Misawa

发明人： Shigetatsu Katori ,  Yukio Maehashi ,  Yukari Misawa

IPC分类号： G06F13/28 ,  G06F13/42 ,  G06F15/17

CPC分类号： G06F13/423 ,  G06F13/28 ,  G06F15/17

摘要： Herein disclosed is a serial data transfer system which has first and second serial data processors connected via a single data line and a single clock line for transferring serial data therebetween. Each of the first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to the data line; and reception confirmation signal detection means for detecting the reception confirmation signal on the data line. The confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to the clock line. Alternatively, the first or second serial data processor includes: an output circuit for outputting a reception confirmation signal to the data line; a circuit for generating a first signal indicating the end of reception of the serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal. When the reception of the serial data on the data line is ended, the output circuit outputs the reception confirmation signal to the data line in synchronism with the first or second signal.

摘要翻译： 这里公开了一种串行数据传输系统，其具有通过单个数据线连接的第一和第二串行数据处理器以及用于在其间传送串行数据的单个时钟线。 第一和第二串行数据处理器中的每一个包括：接收确认信号输出装置，用于向数据线输出接收确认信号; 以及接收确认​​信号检测装置，用于检测数据线上的接收确认信号。 与输出到时钟线的串行时钟脉冲同步执行数据传送的确认。 或者，第一或第二串行数据处理器包括：输出电路，用于向数据线输出接收确认信号; 用于产生指示串行数据的接收结束的第一信号的电路; 用于产生指示所接收的数据的处理结束的第二信号的电路; 以及用于控制所述接收确认信号的输出的电路。 当数据线上的串行数据的接收结束时，输出电路与第一或第二信号同步地向数据线输出接收确认信号。

公开(公告)号：US5159688A

公开(公告)日：1992-10-27

申请号：US691284

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

公开(公告)号：US4847867A

公开(公告)日：1989-07-11

申请号：US91803

申请日：1987-09-01

申请人： Masaki Nasu ,  Shigetatsu Katori ,  Yukio Maehashi ,  Kazutoshi Yoshizawa

发明人： Masaki Nasu ,  Shigetatsu Katori ,  Yukio Maehashi ,  Kazutoshi Yoshizawa

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4077 ,  G06F13/4256

摘要： A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.

摘要翻译： 公开了一种串行数据通信系统。 该系统包括通过单个时钟线和单个数据线互连的多个站。 站中的主站包括用于驱动时钟线的晶体管推挽电路，以在时钟线上输出时钟信号。 因此，时钟信号具有尖锐的引导和下降沿。 数据线耦合到线逻辑装置。 发送站与时钟信号的相关联的时钟脉冲的前沿和下降沿中的一个同步地在数据线上传输数据信号的每一位，并且接收站与另一个的同步接收数据信号的每一位 相关时钟脉冲的前沿和下降沿。

公开(公告)号：US5163150A

公开(公告)日：1992-11-10

申请号：US691297

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行和中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新启动由中断到堆栈存储器的程序执行所必需的信息的堆栈操作。 虽然处理器可以在没有堆栈操作的情况下响应于第二模式信号执行中断操作，从而可以提供具有较少开销的改进的处理器。

公开(公告)号：US5036458A

公开(公告)日：1991-07-30

申请号：US287622

申请日：1988-12-20

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.

摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新执行由堆栈存储器中的中断而停止的程序所需的信息的堆栈操作。 处理器可以在不进行堆栈操作的情况下响应于第二模式信号执行中断操作，从而提供具有较少开销的改进的处理器。 在多种应用中描述了两种中断模式技术，包括D / A转换，串行数据传输和接收以及计算机外围设备的操作。

公开(公告)号：US4839797A

公开(公告)日：1989-06-13

申请号：US759006

申请日：1985-07-25

申请人： Shigetatsu Katori ,  Yukio Maehashi

发明人： Shigetatsu Katori ,  Yukio Maehashi

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/455

CPC分类号： G06F9/30174 ,  G06F9/30189

摘要： A microprocessor includes a central processing unit which executes a program according to at least one control signal generated by an instruction decoder. The instruction decoder is designed such that a first type instruction compatible for the central processing unit can be decoded. A second type instruction not compatible for the central processing unit is applied as an address to a conversion memory in which a first type instruction corresponding in function to the second type instruction has been stored. The first type instruction in the conversion memory is then applied to the instruction decoder instead of the second type instruction. Thus, the second type instruction can be executed by the central processing unit which is not otherwise compatible with the second type instruction.

摘要翻译： 微处理器包括中央处理单元，该中央处理单元根据由指令解码器产生的至少一个控制信号来执行程序。 指令解码器被设计成使得能够解码与中央处理单元兼容的第一类型指令。 将不兼容中央处理单元的第二类型指令作为地址应用于其中已经存储了与第二类型指令功能相对应的第一类型指令的转换存储器。 然后转换存储器中的第一类型指令被施加到指令解码器而不是第二类型指令。 因此，第二类型的指令可以由与第二类型指令不兼容的中央处理单元执行。

公开(公告)号：US08742804B2

公开(公告)日：2014-06-03

申请号：US13473658

申请日：2012-05-17

申请人： Masashi Fujita ,  Yukio Maehashi

发明人： Masashi Fujita ,  Yukio Maehashi

IPC分类号： H03B19/06

CPC分类号： H03K3/356156 ,  H03K21/023 ,  H03K23/44 ,  H03K23/52

摘要： A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.

摘要翻译： 提供具有低功耗和小面积的半导体器件。 通过使用包括用于沟道的氧化物半导体的晶体管作为包括在触发器电路中的晶体管，可以实现晶体管数量少，功耗低，面积小的分压电路。 通过使用分压电路，可以提供稳定运转且高可靠性的半导体装置。

公开(公告)号：US5287471A

公开(公告)日：1994-02-15

申请号：US556484

申请日：1990-07-24

申请人： Tsuyoshi Katayose ,  Yukio Maehashi

发明人： Tsuyoshi Katayose ,  Yukio Maehashi

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： A data transfer controller for controlling DMA data transfer between a memory area and a peripheral unit. The data transfer controller has a first register which stores address information relative to a predetermined address of the memory area. A DMA control unit uses the first register and a second register to perform the DMA data transfer between the memory area and the peripheral unit. The data transfer controller also has a third register for storing data used for accessing the memory area of the DMA transfer. An updater is used to update the contents of the third register whenever a memory access uses the third register and is different from a memory access associated with data transfer between the memory area and the peripheral unit. Finally, a counter changes the contents of the third register in one direction whenever the data transfer between the memory area and the peripheral unit is performed. The counter changes the contents of the third register in an opposite direction whenever memory access using the third register is performed.

摘要翻译： 一种数据传输控制器，用于控制存储区和外设之间的DMA数据传输。 数据传输控制器具有第一寄存器，其存储相对于存储器区域的预定地址的地址信息。 DMA控制单元使用第一寄存器和第二寄存器来执行存储器区域和外围单元之间的DMA数据传输。 数据传输控制器还具有用于存储用于访问DMA传输的存储区域的数据的第三寄存器。 只要存储器访问使用第三寄存器并且与存储器区域和外围单元之间的数据传输相关联的存储器访问不同，更新器被用于更新第三寄存器的内容。 最后，每当执行存储器区域和外围单元之间的数据传输时，计数器在一个方向上改变第三寄存器的内容。 当执行使用第三个寄存器的存储器访问时，计数器以相反的方向改变第三寄存器的内容。

公开(公告)号：US4953082A

公开(公告)日：1990-08-28

申请号：US310577

申请日：1989-02-15

申请人： Masahiro Nomura ,  Yukio Maehashi

发明人： Masahiro Nomura ,  Yukio Maehashi

IPC分类号： G06F15/167 ,  G06F9/38 ,  G06F9/44 ,  G06F15/82

CPC分类号： G06F9/3889 ,  G06F9/3879 ,  G06F9/4436

摘要： An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having a sequence control information and a data to be processed.

公开(公告)号：US4930068A

公开(公告)日：1990-05-29

申请号：US118671

申请日：1987-11-09

申请人： Tsuyoshi Katayose ,  Yukio Maehashi

发明人： Tsuyoshi Katayose ,  Yukio Maehashi

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： A data processor comprises an interrupt processing request controller receiving processing requests from peripheral devices for generating an interrupt request. An execution unit has a first mode of executing the interrupt processing in accordance with a user's program and a second mode of executing the interrupt processing in accordance with a microprogram while maintaining an internal condition concerning execution of a program. The controller operates to selectively inhibit the execution of the interrupt processing in the first mode, but to basically allow the execution of the interrupt processing in the second mode.

摘要翻译： 数据处理器包括接收来自外围设备的处理请求以产生中断请求的中断处理请求控制器。 执行单元具有根据用户程序执行中断处理的第一模式和根据微程序执行中断处理的第二模式，同时保持关于程序执行的内部条件。 控制器操作以选择性地禁止第一模式中的中断处理的执行，而基本上允许在第二模式中执行中断处理。