公开(公告)号：US20130264632A1

公开(公告)日：2013-10-10

申请号：US13812070

申请日：2012-04-24

申请人： Shijin Ding ,  Sun Chen ,  Xingmei Cui ,  Pengfei Wang ,  Wei Zhang

发明人： Shijin Ding ,  Sun Chen ,  Xingmei Cui ,  Pengfei Wang ,  Wei Zhang

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L29/66742 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： The invention relates to a thin film transistor memory and its fabricating method, This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulting layer and the second layer metal nanocrystals grown by ALD method. in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown. by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method. The TFT memory in this invention has the advantage with large P/E window, good data retention, high P/E speed, stable threshold voltage and simple fabricating process.

摘要翻译： 本发明涉及薄膜晶体管存储器及其制造方法，从底部到顶部使用基板作为栅电极的存储器包括电荷阻挡层，电荷存储层，电荷隧道层，器件的有源区和 源/漏电极。 电荷阻挡层是ALD生长的Al 2 O 3膜。 电荷存储层是由ALD法生长的第一层金属纳米晶体，绝缘层和第二层金属纳米晶体的两层金属纳米晶体。 从下到上。 电荷隧道层是包括生长的SiO 2 / HfO 2 / SiO 2或Al 2 O 3 / HfO 2 / Al 2 O 3膜的对称堆叠层。 通过ALD方法从下到上依次。 器件的有源区是通过RF溅射法生长的IGZO膜，并且通过标准光刻和湿蚀刻法形成。 本发明的TFT存储器具有P / E窗口大，数据保持性好，P / E速度高，阈值电压稳定，制造工艺简单的优点。

公开(公告)号：US20120309118A1

公开(公告)日：2012-12-06

申请号：US13304149

申请日：2011-11-23

申请人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

发明人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

IPC分类号： H01L21/66

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593

摘要： A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.

摘要翻译： 公开了用于高完整性封装技术领域的硅通孔互连中使用的硅晶片对准方法。 在一个方面，该方法包括对准和校准上下硅晶片，电子层叠和互连，以提高硅晶片的对准精度并降低互连电阻。 在一些实施例中，通过该方法制造的集成电路芯片提高了速度和能量性能。

公开(公告)号：US20120273866A1

公开(公告)日：2012-11-01

申请号：US13322640

申请日：2010-12-24

申请人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

发明人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

IPC分类号： H01L29/792

CPC分类号： H01L21/28273 ,  H01L27/11521

摘要： A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (107); one drain region (108) of a first doping type; two source regions (101a,101b) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices. and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.

摘要翻译： 提供了一种具有埋地漏极的半导体存储器件。 该器件包括半导体衬底（107）; 一个第一掺杂类型的漏极区域（108）; 具有第二掺杂类型的两个源极区域（101a，101b） 以及设置在半导体基板上用于捕获电子的堆叠栅极。 由多个半导体存储器件形成的存储器阵列。 还提供了其制造方法。 半导体存储器件具有电池面积小，制造工艺简单等优点。 存储器件的制造成本降低，并且存储器件的存储密度增加。

公开(公告)号：US20120182063A1

公开(公告)日：2012-07-19

申请号：US13498778

申请日：2011-04-21

申请人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

发明人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

IPC分类号： H01L31/167

CPC分类号： H01L31/1136 ,  H01L31/167

摘要： The present invention belongs to the technical field of semiconductor devices, and discloses a power device using photoelectron injection to modulate conductivity and the method thereof. The power device comprises at least one photoelectron injection light source and a power MOS transistor. The present invention uses photoelectron injection method to inject carriers to the drift region under the gate of the power MOS transistor, thus modulating the conductivity and further decreasing the specific on-resistance of the power MOS transistor. Moreover, as the doping concentration of the drift region can be decreased and the blocking voltage can be increased, the performance of the power MOS transistor can be greatly improved and the application of power MOS transistor can be expanded to high-voltage fields.

摘要翻译： 本发明属于半导体器件的技术领域，并且公开了使用光电子注入来调节电导率的功率器件及其方法。 功率器件包括至少一个光电子注入光源和功率MOS晶体管。 本发明使用光电子注入方法将载流子注入功率MOS晶体管的栅极下方的漂移区域，从而调制导电率并进一步降低功率MOS晶体管的比导通电阻。 此外，随着漂移区域的掺杂浓度可以降低并且可以提高阻挡电压，可以大大提高功率MOS晶体管的性能，并且可以将功率MOS晶体管的应用扩展到高电压场。

公开(公告)号：US08994095B2

公开(公告)日：2015-03-31

申请号：US13322640

申请日：2010-12-24

申请人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

发明人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L21/28273 ,  H01L27/11521

摘要： A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (107); one drain region (108) of a first doping type; two source regions (101a, 101b) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.

摘要翻译： 提供了一种具有埋地漏极的半导体存储器件。 该器件包括半导体衬底（107）; 一个第一掺杂类型的漏极区域（108）; 具有第二掺杂类型的两个源极区域（101a，101b） 以及设置在半导体基板上用于捕获电子的堆叠栅极。 还提供了由多个半导体存储器件形成的存储器阵列及其制造方法。 半导体存储器件具有电池面积小，制造工艺简单等优点。 存储器件的制造成本降低，并且存储器件的存储密度增加。

公开(公告)号：US08932929B2

公开(公告)日：2015-01-13

申请号：US13812070

申请日：2012-04-24

申请人： Shijin Ding ,  Sun Chen ,  Xingmei Cui ,  Pengfei Wang ,  Wei Zhang

发明人： Shijin Ding ,  Sun Chen ,  Xingmei Cui ,  Pengfei Wang ,  Wei Zhang

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L29/66742 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： The invention relates to a thin film transistor memory and its fabricating method. This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulating layer and the second layer metal nanocrystals grown by ALD method in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method. The TFT memory in this invention has the advantage with large P/E window, good data retention, high P/E speed, stable threshold voltage and simple fabricating process.

摘要翻译： 本发明涉及薄膜晶体管存储器及其制造方法。 从底部到顶部使用基板作为栅电极的这种存储器包括电荷阻挡层，电荷存储层，电荷隧道层，器件的有源区和源极/漏极。 电荷阻挡层是ALD生长的Al 2 O 3膜。 电荷存储层是包括第一层金属纳米晶体，绝缘层和第二层金属纳米晶体的两层金属纳米晶体，其由ALD方法依次从下到上生长。 电荷隧穿层是对称的堆叠层，其包括通过ALD法从下到上生长的SiO 2 / HfO 2 / SiO 2或Al 2 O 3 / HfO 2 / Al 2 O 3膜。 器件的有源区是通过RF溅射法生长的IGZO膜，并且通过标准光刻和湿蚀刻法形成。 本发明的TFT存储器具有P / E窗口大，数据保持性好，P / E速度高，阈值电压稳定，制造工艺简单的优点。

公开(公告)号：US20130062684A1

公开(公告)日：2013-03-14

申请号：US13518306

申请日：2011-05-24

申请人： Shijin Ding ,  Hongyan Gou ,  Wei Zhang

发明人： Shijin Ding ,  Hongyan Gou ,  Wei Zhang

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： C23C16/45525 ,  B82Y10/00 ,  C23C16/40 ,  H01L21/28079 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/495

摘要： The invention relates to a gate stack structure suitable for use in a semiconductor flash memory device and its fabricating method. The gate stack structure is fabricated on a p-type 100 silicon substrate, which also includes the following components in sequence from bottom to top: a charge tunnel layer of Al2O3 film, the first charge trapping layer of RuOx nanocrystals; the second charge trapping layer of high-k HxAlyOz film, a charge blocking layer of Al2O3 film, and a top electrode. In this invention, the RuOx nanocrystals have excellent thermal stability, and do not diffuse easily at high temperatures. The high-k HfxAlyOz film has high density charge traps.Pd with a high work function is used as the top electrode. Therefore, the present gate stack structure has vast practical prospects for nanocrystal memory devices.

摘要翻译： 本发明涉及一种适用于半导体闪速存储器件的栅极堆叠结构及其制造方法。 栅极堆叠结构是在p型100硅衬底上制造的，该衬底还从底部到顶部依次包括以下部件：AlO 2膜的电荷隧道层，RuOx纳米晶体的第一电荷俘获层; 高k HxAlyOz膜的第二电荷俘获层，Al 2 O 3膜的电荷阻挡层和顶电极。 在本发明中，RuOx纳米晶体具有优异的热稳定性，并且在高温下不易扩散。 高k HfxAlyOz薄膜具有高密度电荷阱。具有高功函数的Pd用作顶电极。 因此，本发明的栅极堆叠结构对于纳米晶体存储器件具有巨大的实践前景。

公开(公告)号：US20120261744A1

公开(公告)日：2012-10-18

申请号：US13378114

申请日：2010-12-24

申请人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

发明人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well.

摘要翻译： 本发明涉及使用窄带隙材料作为源电极材料的半导体器件，特别是隧道场效应晶体管（TFET）。 作为隧道场效应晶体管型半导体器件的半导体器件，其中源材料被表征为窄带隙材料; 同时，还有一个U槽通道。 窄带隙材料导致驱动电流的升高和U沟道沟道减少漏极漏电流。 本发明公开的TFET具有漏电流低，驱动电流高，集成度高的优点。 通过使用本发明，静电消耗也降低了。 整合密度也提高了。