公开(公告)号：US20060034133A1

公开(公告)日：2006-02-16

申请号：US10534049

申请日：2002-11-08

申请人： Tomonori Sekiguchi ,  Shinichi Myatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Shinichi Myatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。