公开(公告)号：US08476132B2

公开(公告)日：2013-07-02

申请号：US12704278

申请日：2010-02-11

申请人： Fujio Masuoka ,  Shintaro Arai

发明人： Fujio Masuoka ,  Shintaro Arai

IPC分类号： H01L21/336

CPC分类号： H01L21/823885 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/7827

摘要： It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.

摘要翻译： 旨在提供一种制造半导体器件的方法，包括以下步骤：在其一侧上提供至少一个半导体柱架的衬底; 形成第一电介质膜以至少部分地覆盖所述至少一个半导体柱的表面; 在所述第一电介质膜上形成导电膜; 通过蚀刻位于上表面上并沿着半导体柱的侧表面的上部的导电膜的一部分去除; 在半导体柱的侧面的上表面和上部的至少一部分上形成保护膜; 蚀刻保护膜以在导电膜和第一电介质膜的各个顶表面上形成保护膜基侧壁，每个顶表面沿着半导体柱的侧表面定位; 形成用于形成栅极线的抗蚀剂图案，使得通过施加抗蚀剂并使用光刻在抗蚀剂图案的至少一部分形成在半导体柱的顶表面上; 并且通过使用抗蚀剂图案作为掩模通过蚀刻导电膜来部分去除，同时通过保护膜侧壁保护沿着半导体柱的侧表面定位的导电膜和第一电介质膜的部分，以形成 栅电极和从栅电极延伸的栅极线。

公开(公告)号：US08395208B2

公开(公告)日：2013-03-12

申请号：US13478359

申请日：2012-05-23

申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

公开(公告)号：US08378425B2

公开(公告)日：2013-02-19

申请号：US12699647

申请日：2010-02-03

申请人： Fujio Masuoka ,  Shintaro Arai

发明人： Fujio Masuoka ,  Shintaro Arai

IPC分类号： H01L21/70 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78642

摘要： It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a CMOS 6T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using six MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area.

摘要翻译： 旨在在包括垂直晶体管SGT的CMOS 6T-SRAM中实现足够小的SRAM单元面积和稳定的操作余量。 在使用六个MOS晶体管构成的静态存储单元中，构成存储单元的MOS晶体管形成在形成于掩埋氧化膜上的平面硅层上，具有漏极，栅极和源极的结构 沿垂直方向布置，其中所述栅极形成为围绕柱状半导体层。 平面硅层包括具有第一导电类型的第一有源区和具有第二导电类型的第二有源区。 第一和第二有源区域通过形成在平面硅层的表面中的硅化物层彼此连接，以实现具有足够小的面积的SRAM单元。

公开(公告)号：US08241976B2

公开(公告)日：2012-08-14

申请号：US12704000

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/8232

CPC分类号： H01L29/78642 ,  H01L22/26

摘要： The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 该方法包括以下步骤：在形成在基板上的氧化膜上形成平面半导体层，然后在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在柱状的第一导电型半导体层周围形成栅极电介质膜和由金属制成的栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层。

公开(公告)号：US08212298B2

公开(公告)日：2012-07-03

申请号：US12704239

申请日：2010-02-11

申请人： Fujio Masuoka ,  Shintaro Arai

发明人： Fujio Masuoka ,  Shintaro Arai

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/10876

摘要： A semiconductor storage device where one MOS transistor in a memory cell section includes a selection transistor, and one MOS transistor in a peripheral circuit section includes a first MOS transistor and a second MOS transistor of different conductivity type, the first MOS and second MOS transistors and the selection transistor include lower drain or source regions in a planar semiconductor layer, a pillar-shaped semiconductor layer on the planar semiconductor layer, upper source or drain regions in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode that surrounds a sidewall of the pillar-shaped semiconductor layer through a dielectric film, and where a first silicide layer connects a surface of the lower drain or source region of the first MOS and second MOS transistors, and a second silicide layer on a surface of the lower drain or source region of the selection transistor.

摘要翻译： 一种半导体存储装置，其中存储单元部分中的一个MOS晶体管包括选择晶体管，并且外围电路部分中的一个MOS晶体管包括第一MOS晶体管和不同导电类型的第二MOS晶体管，第一MOS和第二MOS晶体管以及 选择晶体管包括平面半导体层中的下部漏极或源极区域，平面半导体层上的柱状半导体层，柱状半导体层的上部中的上部源极或漏极区域以及围绕 通过介电膜形成柱状半导体层的侧壁，其中第一硅化物层连接第一MOS和第二MOS晶体管的下部漏极或源极区域的表面，以及在下部表面的第二硅化物层 漏极或源极区域。

公开(公告)号：US08158468B2

公开(公告)日：2012-04-17

申请号：US12703991

申请日：2010-02-11

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

IPC分类号： H01L21/8232 ,  H01L29/786

CPC分类号： H01L29/458 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642

摘要： Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 公开了一种半导体器件制造方法，其包括以下步骤：在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在所述柱状的第一导电型半导体层周围形成具有金属膜和非晶硅或多晶硅膜的叠层结构的栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成第一和第二侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成金属 - 半导体化合物; 在栅电极上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成接触; 并且在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成接触。

公开(公告)号：US08138048B2

公开(公告)日：2012-03-20

申请号：US12704012

申请日：2010-02-11

申请人： Fujio Masuoka ,  Shintaro Arai

发明人： Fujio Masuoka ,  Shintaro Arai

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642

摘要： It is intended to provide a semiconductor device having a reduced thickness of a silicon nitride film on an outer periphery of a gate electrode of an SGT. A semiconductor device of the present invention is constructed using a MOS transistor which has a structure where a drain, a gate and a source are arranged in a vertical direction with respect to a substrate, and the gate is formed to surround a pillar-shaped semiconductor layer. The semiconductor device comprises: a silicide layer formed in an upper surface of each of upper and lower diffusion layers formed in upper and underneath portions of the pillar-shaped semiconductor layer, in a self-alignment manner, wherein the silicide layer is formed after forming a first dielectric film on a sidewall of the pillar-shaped semiconductor layer to protect the sidewall of the pillar-shaped semiconductor layer during formation of the silicide layer; and a second dielectric film formed, after forming the silicide layer and then removing the first dielectric film, in such a manner as to cover a source/drain region formed in the underneath portion of the pillar-shaped semiconductor layer, the gate electrode formed on the sidewall of the pillar-shaped semiconductor layer, and a source/drain region formed on the upper portion of the pillar-shaped semiconductor layer.

摘要翻译： 旨在提供一种在SGT的栅电极的外周上具有减小的氮化硅膜厚度的半导体器件。 本发明的半导体器件使用具有以下结构的MOS晶体管构成：漏极，栅极和源极相对于衬底在垂直方向上排列，并且栅极形成为包围柱状半导体 层。 半导体器件包括：硅化物层，其以自对准方式形成在形成在柱状半导体层的上部和下部的上部和下部扩散层的上表面的上表面中，其中在形成后形成硅化物层 柱状半导体层的侧壁上的第一电介质膜，用于在形成硅化物层期间保护柱状半导体层的侧壁; 以及第二电介质膜，在形成硅化物层然后除去第一电介质膜之后，以覆盖形成在柱状半导体层的下部的源极/漏极区域的方式形成第二电介质膜，形成在 柱状半导体层的侧壁和形成在柱状半导体层的上部的源极/漏极区域。

公开(公告)号：US08080458B2

公开(公告)日：2011-12-20

申请号：US12761735

申请日：2010-04-16

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  Navab Singh ,  Kavitha Devi Buddharaju ,  Shen Nansheng ,  Rukmani Devi Sayanthan

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  Navab Singh ,  Kavitha Devi Buddharaju ,  Shen Nansheng ,  Rukmani Devi Sayanthan

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66666 ,  H01L29/78642

摘要： A method of manufacturing a semiconductor device includes the steps of forming a first columnar semiconductor layer on a substrate forming a first flat semiconductor layer forming a first semiconductor layer of a second conductive type, and forming a first insulating film. The method further includes the steps of forming a gate insulating film and a gate electrode, forming a second semiconductor layer of the second conductive type, forming a semiconductor layer of a first conductive type and forming a metal-semiconductor compound. The first insulating film has a thickness larger than that of the gate insulating film formed around the first columnar silicon layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在形成第二导电类型的第一半导体层的第一平坦半导体层的基板上形成第一柱状半导体层，形成第一绝缘膜。 该方法还包括形成栅绝缘膜和栅电极，形成第二导电类型的第二半导体层的步骤，形成第一导电类型的半导体层并形成金属半导体化合物。 第一绝缘膜的厚度大于围绕第一柱状硅层形成的栅极绝缘膜的厚度。

公开(公告)号：US20110260259A1

公开(公告)日：2011-10-27

申请号：US13090726

申请日：2011-04-20

申请人： Fujio Masuoka ,  Shintaro Arai

发明人： Fujio Masuoka ,  Shintaro Arai

IPC分类号： H01L27/092

CPC分类号： H01L21/823885 ,  H01L27/0207 ,  H01L27/092

摘要： The CMOS inverter coupled circuit is composed of CMOS inverters using SGTs and series-connected in two or more stages. Multiple CMOS inverters share source diffusion layers on a substrate. The CMOS inverters different in the structure of a contact formed on gate wires are alternately arranged next to each other. The CMOS inverters are provided at the minimum intervals. The output terminal of a CMOS inverter is connected to the wiring layer of the next-stage CMOS inverter via the contact of the next-stage CMOS inverter.

摘要翻译： CMOS反相器耦合电路由使用SGT的CMOS反相器组成，并串联连接两个或多个阶段。 多个CMOS反相器在基板上共享源极扩散层。 形成在栅极线上的触点的结构不同的CMOS反相器彼此交替布置。 以最小的间隔提供CMOS反相器。 CMOS反相器的输出端子通过下一级CMOS反相器的接触连接到下一级CMOS反相器的布线层。

公开(公告)号：US20110062523A1

公开(公告)日：2011-03-17

申请号：US12881554

申请日：2010-09-14

申请人： Fujio Masuoka ,  Shintaro Arai

发明人： Fujio Masuoka ,  Shintaro Arai

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L27/0207 ,  H01L21/823814 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/11 ,  H01L29/1083

摘要： In a static memory cell composed of four MOS transistors, the transistors composing a memory cell are formed on a substrate and have a drain, gate, and source arranged vertically with the gate surrounding a columnar semiconductor layer. In this memory cell, the first diffusion layers (second diffusion layers) functioning as a first memory node (second memory node) are connected via a first silicide layer (second silicide layer) formed on their surfaces, whereby an SRAM cell having a small area is realized. Furthermore, a first anti-leak diffusion layer (second anti-leak diffusion layer) having the conductivity type opposite to the first well is formed between the first well and the first diffusion layer (second diffusion layer) having the same conductivity type as the first well so as to prevent leak to the substrate.

摘要翻译： 在由四个MOS晶体管组成的静态存储单元中，构成存储单元的晶体管形成在衬底上，并且具有围绕柱状半导体层的栅极垂直排列的漏极，栅极和源极。 在该存储单元中，用作第一存储器节点（第二存储器节点）的第一扩散层（第二扩散层）经由其表面上形成的第一硅化物层（第二硅化物层）连接，由此形成具有小面积的SRAM单元 实现了。 此外，在第一阱和具有与第一阱相同的导电类型的第一扩散层（第二扩散层）之间形成具有与第一阱相反的导电类型的第一防漏扩散层（第二防漏扩散层） 以防止泄漏到基板。