公开(公告)号：US06734523B2

公开(公告)日：2004-05-11

申请号：US09395184

申请日：1999-09-14

申请人： Shuuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda

发明人： Shuuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda

IPC分类号： H01L2900

CPC分类号： H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  Y10S257/903

摘要： A semiconductor device including a well divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film is formed such as to have to a depth from the main surface of a semiconductor substrate, and the area from the main surface of the substrate to the depth is divided into a plurality of first regions. A first well is formed in each of the first regions. A second well is formed in a second region deeper than the first well in the substrate, and the second well is in contact with some of the first wells.

摘要翻译： 一种半导体器件，其包括通过沟槽被细分为多个部分，以实现布局面积的减小及其制造方法。 在半导体器件中，元件隔离膜形成为具有从半导体衬底的主表面的深度，并且从衬底的主表面到深度的区域被分成多个第一区域。 在每个第一区域中形成第一孔。 第二阱形成在比衬底中的第一阱更深的第二区域中，并且第二阱与一些第一阱接触。

公开(公告)号：US06475844B1

公开(公告)日：2002-11-05

申请号：US09629485

申请日：2000-07-31

申请人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

发明人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L21/28518 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/4983 ,  H01L29/66659

摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

摘要翻译： 当扩散区域（7a）连接到位线并且扩散区域（8a）连接到栅极电极（3a）的远离存储节点的表面的一部分中时，形成硅化区域（11a） 存储节点。 在与位线连接的扩散区域（7a）的表面形成硅化区域（12a）。 提供一种MOSFET，其抑制从存储节点到栅电极的漏电流并且降低连接到位线的扩散区域的电阻和所述栅电极的电阻。

公开(公告)号：US6162668A

公开(公告)日：2000-12-19

申请号：US260737

申请日：1999-03-03

申请人： Hidekazu Oda ,  Tomohiro Yamashita

发明人： Hidekazu Oda ,  Tomohiro Yamashita

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/762 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/0847 ,  H01L21/28512 ,  H01L21/76216 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7834

摘要： A high withstand voltage semiconductor device includes a semiconductor substrate of a first conductivity type, a metallic wiring formed on a surface of the semiconductor substrate and having a contact face with said semiconductor substrate, a highly doped impurity region formed within the semiconductor substrate below the contact face and of a second conductivity type, a lightly doped impurity region formed around the highly doped impurity region and of the second conductivity type, and a MOSFET with a second conductivity-type having a source or drain region formed on the surface of the semiconductor substrate and electrically connected to the metallic wiring through the impurity regions.

摘要翻译： 高耐压半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底的表面上并具有与所述半导体衬底的接触面的金属布线，形成在半导体衬底下方的高度掺杂杂质区域 面和第二导电类型，形成在高掺杂杂质区域和第二导电类型周围的轻掺杂杂质区域，以及形成在半导体衬底的表面上的具有源极或漏极区域的第二导电类型的MOSFET 并通过杂质区域与金属布线电连接。

公开(公告)号：US6130463A

公开(公告)日：2000-10-10

申请号：US346999

申请日：1999-07-02

申请人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

发明人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/49 ,  H01L21/441

CPC分类号： H01L27/10852 ,  H01L21/28518 ,  H01L27/10894 ,  H01L29/4983 ,  H01L29/66659 ,  H01L27/10873 ,  H01L27/10888

摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

公开(公告)号：US20140035055A1

公开(公告)日：2014-02-06

申请号：US14111549

申请日：2012-04-09

申请人： Hirofumi Shinohara ,  Yukio Nishida ,  Katsuyuki Horita ,  Tomohiro Yamashita ,  Hidekazu Oda

发明人： Hirofumi Shinohara ,  Yukio Nishida ,  Katsuyuki Horita ,  Tomohiro Yamashita ,  Hidekazu Oda

IPC分类号： H01L27/088 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/66477

摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.

摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。 这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。 因此，通过在High-k栅极绝缘膜上形成各种阈值电压调整金属膜并将膜分量从它们引入到高k栅极绝缘膜中来控制阈值电压。 然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。 根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。

公开(公告)号：US20080308869A1

公开(公告)日：2008-12-18

申请号：US12194631

申请日：2008-08-20

申请人： Hidekazu ODA ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu ODA ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/00

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered.The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US20070111427A1

公开(公告)日：2007-05-17

申请号：US11599382

申请日：2006-11-15

申请人： Tomohiro Yamashita ,  Yukio Nishida ,  Hidekazu Oda

发明人： Tomohiro Yamashita ,  Yukio Nishida ,  Hidekazu Oda

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7843

摘要： The semiconductor device which can apply the stress application technology to a channel part by a liner film to MISFET including a full silicidation gate electrode, and its manufacturing method are realized. The first liner silicon nitride film is formed on the semiconductor substrate MISFET formed. Insulating films, such as a silicon oxide film, are formed on the first liner silicon nitride film so that it may fully fill up the side of a gate electrode. Next, flattening processing is performed to an insulating film and the first liner silicon nitride film, and a polysilicon gate electrode is exposed. An insulating film is removed leaving the first liner silicon nitride film. The full silicidation of the exposed gate electrode is done, and the second liner silicon nitride film that covers the first liner silicon nitride film and the exposed full silicidation gate electrode is formed.

摘要翻译： 实现了通过衬垫膜将应力施加技术应用于包括全硅化物栅电极的MISFET在内的半导体器件及其制造方法。 第一衬里氮化硅膜形成在形成的半导体衬底MISFET上。 在第一衬垫氮化硅膜上形成诸如氧化硅膜的绝缘膜，使得其可以完全填满栅电极的侧面。 接着，对绝缘膜进行平坦化处理，露出第一衬垫氮化硅膜和多晶硅栅电极。 除去留下第一衬里氮化硅膜的绝缘膜。 完成暴露的栅电极的全硅化，形成覆盖第一衬垫氮化硅膜和暴露的全硅化栅电极的第二衬垫氮化硅膜。

公开(公告)号：US20070007602A1

公开(公告)日：2007-01-11

申请号：US11478669

申请日：2006-07-03

申请人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/94

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US06469347B1

公开(公告)日：2002-10-22

申请号：US09553487

申请日：2000-04-20

申请人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

发明人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

IPC分类号： H01L2976

CPC分类号： H01L29/7838 ,  H01L21/761 ,  H01L21/823807 ,  H01L29/1083

摘要： MOS type semiconductor device is formed on the primary surface of a semiconductor substrate. A channel region includes a punch-through stopper layer, a lower counter-doped layer, and an upper counter-doped layer. The punch-through stopper layer is formed between the source region and the drain region and has a first concentration peak. The lower counter-doped layer is formed between the source region and the drain region, and has a second concentration peak at a position shallower than the position of the first concentration peak. Further, the upper counter-doped layer is formed between the source region and the drain region, and has a third concentration peak at a position shallower than the position of the second concentration peak. A buried-channel semiconductor device exhibits high punch-through characteristics and prevents an increase in a threshold voltage.

摘要翻译： MOS半导体器件形成在半导体衬底的主表面上。 沟道区域包括穿通阻止层，下反向掺杂层和上反相掺杂层。 穿通阻止层形成在源极区域和漏极区域之间，并且具有第一浓度峰值。 下部反掺杂层形成在源极区域和漏极区域之间，并且在比第一浓度峰值位置浅的位置处具有第二浓度峰值。 此外，上部反掺杂层形成在源极区域和漏极区域之间，并且在比第二浓度峰值的位置浅的位置处具有第三浓度峰值。 掩埋沟道半导体器件具有高穿透特性并防止阈值电压的增加。

公开(公告)号：US5978294A

公开(公告)日：1999-11-02

申请号：US112506

申请日：1998-07-09

申请人： Shuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda ,  Shigeki Komori

发明人： Shuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda ,  Shigeki Komori

IPC分类号： G01R31/28 ,  G11C7/14 ,  G11C11/401 ,  G11C11/406 ,  G11C29/12 ,  G11C29/24 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/02 ,  G11C11/24

CPC分类号： G11C7/14 ,  G11C11/406 ,  G11C29/24

摘要： A dummy cell part includes a capacitor having a first end which is connected to one of a plurality of pads and a P-N junction element having a first end which is connected to one of the plurality of pads and a second end which is connected to one of the plurality of pads . A sense part is connected to a second end of the capacitor , for sensing a potential on the second end of the capacitor and outputting the result of sensing to one of the plurality of pads . Thus, a memory cell evaluation semiconductor device which can evaluate a single memory cell, a method of fabricating the same and a memory cell evaluation method are obtained.

摘要翻译： 虚设单元部分31包括具有连接到多个焊盘<2>中的一个的第一端的电容器<311>和具有连接到多个焊盘中的一个的第一端的PN结元件<312> 的焊盘<2>和连接到多个焊盘<2>之一的第二端。 感测部分<32>连接到电容器<311>的第二端，用于感测电容器<311>的第二端上的电位，并将感测结果输出到多个焊盘<2>之一。 因此，可以获得能够评估单个存储单元的存储单元评估半导体器件，其制造方法和存储单元评估方法。