公开(公告)号：US4703284A

公开(公告)日：1987-10-27

申请号：US861036

申请日：1986-05-08

申请人： Stefan Barbu

发明人： Stefan Barbu

IPC分类号： H03F3/189 ,  H03F3/195 ,  H03F3/45 ,  H03F3/68

CPC分类号： H03F3/195

摘要： The invention relates to a high-frequency amplifier which comprises only two cascaded differential stages. The collectors of the transistors (T.sub.1, T.sub.2) of the differential input stage are connected to the emitters of two transistors (T.sub.3, T.sub.4) which have feedback between their collectors and bases and which are biased by means of resistors (R.sub.1, R.sub.2). This input stage forms a resonant circuit. The differential output stage comprises transistors (T.sub.6 and T.sub.7) whose emitters are interconnected by a phase-lead capacitor (C.sub.1) and two resistors (R.sub.8, R.sub.9). Such an arrangement enables a high gain to be obtained over the entire operating frequency range of the amplifier and in particular for high frequencies.

摘要翻译： 本发明涉及仅包括两个级联差分级的高频放大器。 差分输入级的晶体管（T1，T2）的集电极连接到两个晶体管（T3，T4）的发射极，它们在它们的集电极和基极之间具有反馈，并且通过电阻（R1，R2）偏置。 该输入级形成谐振电路。 差分输出级包括晶体管（T6和T7），其发射极由相引线电容器（C1）和两个电阻器（R8，R9）互连。 这种布置使得能够在放大器的整个工作频率范围内获得高增益，特别是对于高频。

公开(公告)号：US4695839A

公开(公告)日：1987-09-22

申请号：US741090

申请日：1985-06-04

申请人： Stefan Barbu ,  Leonardus Valkestijn ,  Franciscus A. M. van de Kerkhof

发明人： Stefan Barbu ,  Leonardus Valkestijn ,  Franciscus A. M. van de Kerkhof

IPC分类号： G06F13/36 ,  G06F13/16 ,  G06F13/20 ,  G06F13/38 ,  G06F13/42 ,  H04Q9/00 ,  H04Q1/00

CPC分类号： G06F13/4291

摘要： A slave-type interface circuit operating with a series bus in a configuration in which writing takes place after recognition of an address. A cycle transmitted by the bus contains an address sequence and a data sequence.The circuit controls a plurality of user circuits (COM) on the basis of data stored in a memory (M) and of a decoder (CDEC).A register (REG) and a bus logic (BUSL) receive at their inputs (L.sub.1, L.sub.2) information (SDA) and clock (SCL) signals. The bus logic (BUSL) receives from an identification circuit (AIC) a signal (DVA) indicating whether or not the address transmitted by the bus corresponds to an address A.sub.0, A.sub.1, A.sub.2 displayed at the inputs S.sub.0, S.sub.1 and S.sub.2. It controls the circuit on the basis of the register (REG) initialization signal (RST1), a signal LDS) for the authorization of the loading of data into the memory (M) and an acceptance signal (ACK) transmitted in the direction of the bus.

摘要翻译： 一种从属型接口电路，其操作与串行总线在配置中，在识别地址之后进行写入。 由总线发送的周期包含地址序列和数据序列。 该电路基于存储在存储器（M）和解码​​器（CDEC）中的数据来控制多个用户电路（COM）。 寄存器（RE​​G）和总线逻辑（BUSL）在其输入（L1，L2）信息（SDA）和时钟（SCL）信号上接收。 总线逻辑（BUSL）从识别电路（AIC）接收指示总线发送的地址是否对应于在输入S0，S1和S2处显示的地址A0，A1，A2的信号（DVA）。 它基于用于授权将数据加载到存储器（M）中的寄存器（RE​​G）初始化信号（RST1），信号LDS）来控制电路，以及接收信号（ACK） 总线。

公开(公告)号：US4903115A

公开(公告)日：1990-02-20

申请号：US119609

申请日：1987-11-12

申请人： Stefan Barbu ,  Claude E. Chapron

发明人： Stefan Barbu ,  Claude E. Chapron

IPC分类号： H01L21/8222 ,  H01L21/28 ,  H01L21/331 ,  H01L21/60 ,  H01L23/485 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L2924/0002

摘要： The invention relates to semiconductor devices comprising logic, or low-noise, transistors, or transistors for very high frequencies whose structure is improved with respect to the dimensions, the series resistance value, and/or the gain. Such semiconductor devices may be integrated into a semiconductor body having surfaces with contact windows covered with layers of metal combined with the material of the semiconductor body. A multi-collector transistor structure is also formed.

公开(公告)号：US4815026A

公开(公告)日：1989-03-21

申请号：US112016

申请日：1987-10-20

申请人： Stefan Barbu ,  Leonardus Valkestijn ,  van de Kerkhof

发明人： Stefan Barbu ,  Leonardus Valkestijn ,  van de Kerkhof

IPC分类号： G06F13/14 ,  G06F13/42 ,  G11B20/10 ,  G06F13/00

CPC分类号： G06F13/4291

摘要： A slave-type interface circuit which can receive signals from a bus if the coding A.sub.0, A.sub.1 and A.sub.2 of its inputs S.sub.0, S.sub.1 and S.sub.2 corresponds to that mode of operation. The signals from the bus are then delivered to the inputs L.sub.1 and L.sub.2. With another mode of operation the coding of inputs S.sub.0, S.sub.1 and S.sub.2 corresponds to off-line operation on the basis of logic levels applied to the same inputs L.sub.1 and L.sub.2. A branching block (SBL) directs the signals from the inputs L.sub.1 and L.sub.2 either to a bus receiver RBUS or directly to a decoder CDEC controlling a group of switches (COM). In the case of operation with a bus, the bus receiver (RBUS) controls the logic for the progress for operations.

摘要翻译： 如果其输入S0，S1和S2的编码A0，A1和A2对应于这种操作模式，则可以从总线接收信号的从属型接口电路。 然后将来自总线的信号传送到输入端L1和L2。 利用另一种操作模式，输入S0，S1和S2的编码基于施加到相同输入L1和L2的逻辑电平对应于离线操作。 分支块（SBL）将来自输入L1和L2的信号引导到总线接收器RBUS或直接指向控制一组开关（COM）的解码器CDEC。 在使用总线的情况下，总线接收器（RBUS）控制用于操作进度的逻辑。

公开(公告)号：US4769616A

公开(公告)日：1988-09-06

申请号：US945416

申请日：1986-12-22

申请人： Stefan Barbu

发明人： Stefan Barbu

IPC分类号： H03F3/189 ,  H03F3/19 ,  H03F3/45 ,  H03G11/00 ,  H03G11/06

CPC分类号： H03F3/45071 ,  H03F3/19 ,  H03F2200/282 ,  H03F2200/285 ,  H03F2203/45022 ,  H03F2203/45051 ,  H03F2203/45176 ,  H03F2203/45202 ,  H03F2203/45221 ,  H03F2203/45274 ,  H03F2203/45458 ,  H03F2203/45464 ,  H03F2203/45471

摘要： A high-frequency differential-amplifier stage. The collectors of the transistors (T.sub.1, T.sub.2) are connected to the emitters of two transistors (T.sub.3, T.sub.4) coupled to provide feedback between their collectors and their bases and which are biased by means of resistors (R.sub.1, R.sub.2). This input stage forms a resonant circuit. Two current sources (R.sub.32, T.sub.32, R.sub.31, T.sub.31) improve the operation of this stage in the saturated mode.

摘要翻译： 高频差分放大器级。 晶体管（T1，T2）的集电极连接到两个晶体管（T3，T4）的发射极，这两个晶体管（T3，T4）耦合以提供它们的集电极和它们的基极之间的反馈，并且通过电阻（R1，R2）偏置。 该输入级形成谐振电路。 两个电流源（R32，T32，R31，T31）改善了饱和模式下该阶段的工作。

公开(公告)号：US4749442A

公开(公告)日：1988-06-07

申请号：US841128

申请日：1986-03-18

申请人： Stefan Barbu ,  Claude E. P. Chapron

发明人： Stefan Barbu ,  Claude E. P. Chapron

IPC分类号： H01L21/8222 ,  H01L21/28 ,  H01L21/331 ,  H01L21/60 ,  H01L23/485 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L2924/0002

摘要： In the method according to the invention conductive electrodes are provided with the aid of a mask aligned with respect to at least two contact windows present in an insulating layer. First, layers of metal combining with semiconductor material, for example, Pt silicide, are provided in the contact windows. A narrow region of the insulating layer between the two contact windows may have a reduced dimension because in their extreme relative positions the conductive electrodes can only partially cover the contact windows. The invention also relates to semiconductor devices comprising logic (or low-noise) transistors, or transistors for very high frequencies whose structure is improved with respect to their dimensions, their series resistance value and/or their gain.

摘要翻译： 在根据本发明的方法中，借助于相对于存在于绝缘层中的至少两个接触窗对准的掩模来提供导电电极。 首先，在接触窗口中设置与半导体材料结合的金属层，例如Pt硅化物。 两个接触窗口之间的绝缘层的窄区域可以具有减小的尺寸，因为在它们的极端相对位置中，导电电极只能部分覆盖接触窗口。 本发明还涉及包括逻辑（或低噪声）晶体管或用于非常高频率的晶体管的半导体器件，其结构相对于它们的尺寸，它们的串联电阻值和/或它们的增益而被改进。