公开(公告)号：US06794293B2

公开(公告)日：2004-09-21

申请号：US09972765

申请日：2001-10-05

申请人： SiYi Li ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  Steve Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

发明人： SiYi Li ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  Steve Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/02126 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76804 ,  H01L21/76808

摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

摘要翻译： 本发明是一种在电介质层内形成沟槽的方法，包括：首先蚀刻电介质层内的通孔。 在蚀刻通孔之后，使用有机插塞来填充通孔的一部分。 在从通孔蚀刻所需量的有机插塞之后，用第一气体混合物蚀刻沟槽至第一深度，并且使用第二气体混合物来进一步将沟槽蚀刻到最终期望的沟槽深度。 优选地，该方法用于不具有中间蚀刻停止层的低k电介质。 另外，优选地，第一气体混合物是聚合气体混合物，第二气体混合物是非聚合气体混合物。 作为使用该方法的结果，产生用于低k电介质的互连结构，而不具有中间蚀刻停止层，该中间蚀刻停止层具有沟槽边缘，其基本上正交，并且具有基本正交的通孔边缘的通孔。

公开(公告)号：US06909195B2

公开(公告)日：2005-06-21

申请号：US10826211

申请日：2004-04-16

申请人： SiYi Li ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  Steve Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

发明人： SiYi Li ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  Steve Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

IPC分类号： H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/31116 ,  H01L21/02126 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76804 ,  H01L21/76808

摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.