摘要:
Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要:
Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
摘要:
Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108) with a plurality of local reference circuits (108a) associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S1) coupled between the staging capacitance and the primary capacitance (130), and a second switching device (S2, S3) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column. The first switching device (S1) couples the staging capacitance (Cs) to the precharged primary capacitance (130) and then isolates the precharged staging capacitance (Cs) from the primary capacitance (130), and the second switching device (S2, S3) isolates the staging capacitance (Cs) from the bitline while the staging capacitance Cs is coupled to the primary capacitance (130), and then couples the precharged staging capacitance (Cs) to the bitline to provide a reference voltage to the bitline during the memory access operation.
摘要翻译:参考发生器系统(108,130)和方法(200)被提供用于为铁电存储器件(102)中的存储器存取操作提供位线参考电压。 参考发生器系统(108,130)包括初级电容(130),对初级电容充电的预充电系统(132)以及具有多个与相应的电压相关联的多个局部参考电路(108a)的参考系统(108) 单独地包括分级电容(Cs)的阵列列,耦合在所述分级电容和所述初级电容(130)之间的第一开关器件(S1)以及耦合在所述分级电容之间的第二开关器件(S 2,S 3) (Cs)和相应阵列列的位线。 第一开关器件(S1)将分级电容(Cs)耦合到预充电的初级电容(130),然后将预充电的分级电容(Cs)与主电容(130)隔离,并且第二开关器件(S2, S 3)将分级电容(Cs)与位线分离,而分级电容Cs耦合到初级电容(130),然后将预充电分级电容(Cs)耦合到位线,以在位线期间向位线提供参考电压 内存访问操作。
摘要:
A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.
摘要:
Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要:
Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
摘要:
Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.
摘要:
A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.
摘要:
An exemplary voice monitoring system includes a wearable voice monitor and an auxiliary device such as a smart phone. The wearable monitor incorporates a wake-on-sound microphone, a vibration motor, and a microcontroller within a small, discreet enclosure. The enclosure can be hung from a necklace chain or affixed to clothing, like a piece of jewelry. The jewelry appearance is enhanced by a removable decorative piece. The microcontroller wakes up in response to a wake signal from the microphone when a voice sound of a wearer is detected. The microcontroller initiates measurements to determine if the voice sound meets preconfigured criteria and activates the vibration motor to alert the wearer. Sound criteria resulting in vibratory alerts are contained in a user-specific schedule tailored according to time of day and day of week. The smart phone can remotely create customized schedules and transmit them to the monitor.
摘要:
Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.