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    Semiconductor memory device and data read method of the same
    2.
    发明申请
    Semiconductor memory device and data read method of the same 失效
    半导体存储器件和数据读取方法相同

    公开(公告)号：US20050122830A1

    公开(公告)日：2005-06-09

    申请号：US10993577

    申请日：2004-11-19

    申请人： Myeong-O Kim ,  Sung-Min Seo

    发明人： Myeong-O Kim ,  Sung-Min Seo

    IPC分类号： G11C11/40 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/04 ,  G11C7/1042 ,  G11C7/1066 ,  G11C2207/2281

    摘要： The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

    摘要翻译： 本发明公开了一种包括第一和第二存储体的半导体存储器件。 第一控制信号产生电路响应外部时钟产生第一控制信号。 第一数据输出电路响应于第一控制信号发送第一输出数据。 内部时钟信号发生电路响应于外部时钟输出第一和第二缓冲时钟信号。 第二控制信号发生电路响应于第一缓冲时钟信号和第一控制信号产生第二控制信号。 第二数据输出电路响应于第二控制信号发送第二输出数据。 第三数据输出电路响应于第一和第二缓冲时钟信号发送第三输出数据。 本发明防止由电源电压和温度变化引起的数据读取错误。

    Sequential activation delay line circuits and methods
    3.
    发明授权
    Sequential activation delay line circuits and methods 有权
    顺序激活延迟线电路和方法

    公开(公告)号：US06815989B2

    公开(公告)日：2004-11-09

    申请号：US10325766

    申请日：2002-12-19

    申请人： Sung-min Seo

    发明人： Sung-min Seo

    IPC分类号： H03L706

    CPC分类号： H03H11/26

    摘要： Delay line circuits and methods include a series of unit delay cells, a respective one of which includes an input and an output that are sequentially connected such that an output of a preceding unit delay cell is connected to an input of a succeeding unit delay cell. At least two of the unit delay cells in the series are sequentially activated in response to an activation signal. The sequential activation may be performed by a control circuit that is connected to the series of unit delay cells.

    摘要翻译： 延迟线电路和方法包括一系列单元延迟单元，其中相应的单元延迟单元包括顺序连接的输入和输出，使得前一单元延迟单元的输出连接到后续单元延迟单元的输入。 串联中的至少两个单元延迟单元响应于激活信号被顺序地激活。 顺序激活可以由连接到一系列单位延迟单元的控制电路来执行。

    Biomaterial detecting device
    5.
    发明授权
    Biomaterial detecting device 有权
    生物材料检测装置

    公开(公告)号：US08871160B2

    公开(公告)日：2014-10-28

    申请号：US13554504

    申请日：2012-07-20

    申请人： Sung-Min Seo ,  Jae-Hyung Park ,  Oleksandrov Sergiy ,  Joong Hwan Lee ,  Mun-Cheol Paek ,  Su-Jin Ku

    发明人： Sung-Min Seo ,  Jae-Hyung Park ,  Oleksandrov Sergiy ,  Joong Hwan Lee ,  Mun-Cheol Paek ,  Su-Jin Ku

    IPC分类号： C40B60/12 ,  B01L3/00

    CPC分类号： B01L3/50853 ,  B01L3/50825 ,  B01L2200/025 ,  B01L2300/046 ,  B01L2300/0609 ,  B01L2300/0636

    摘要： Provided is a biomaterial detecting device for confirming or detecting a biomaterial reaction, and more particularly to a biomaterial detecting device, which is formed in a stick type to thereby be immersed in a tube containing a biomaterial solution to be tested; has an upper portion with a cap structure to thereby induce reaction with a biomaterial, and thus facilitate confirmation and detection of the biomaterial; and is formed in a cap structure to thereby prevent evaporation of a sample and infiltration of an external material at the time of a biomaterial reaction in the tube, and thus improve reliability in analysis.

    摘要翻译： 提供一种用于确认或检测生物材料反应的生物材料检测装置，更具体地说，涉及一种生物材料检测装置，其以棒状形式形成，从而浸入含有待测试的生物材料溶液的管中; 具有帽结构的上部，从而诱导与生物材料的反应，从而促进生物材料的确认和检测; 并且形成为帽结构，从而防止样品的蒸发和管中的生物材料反应时的外部材料的渗透，从而提高分析的可靠性。

    BIO-REACTION DEVICE CHIP
    6.
    发明申请
    BIO-REACTION DEVICE CHIP 审中-公开
    生物反应装置芯片

    公开(公告)号：US20130225445A1

    公开(公告)日：2013-08-29

    申请号：US13554170

    申请日：2012-07-20

    申请人： Sung-Min SEO ,  Jae-Hyung PARK ,  Sergiy Oleksandrov ,  Joong Hwan LEE ,  Mun·Cheol PAEK ,  Su-Jin KU

    发明人： Sung-Min SEO ,  Jae-Hyung PARK ,  Sergiy Oleksandrov ,  Joong Hwan LEE ,  Mun·Cheol PAEK ,  Su-Jin KU

    IPC分类号： C40B40/06 ,  B01L3/00 ,  C40B40/10

    CPC分类号： B01L3/50851 ,  B01L7/52 ,  B01L2200/12 ,  B01L2200/142 ,  B01L2300/04 ,  B01L2300/0636 ,  B01L2300/0829 ,  B01L2300/0851 ,  B01L2300/16

    摘要： Provided is a bio-reaction device chip for confirming or detecting a biomaterial reaction, and more particularly, is a bio-reaction device chip, where a plurality of wells are formed in the plate to contain biomaterials to be tested, thereby simultaneously analyzing various targets, and the well is formed to have a structure of two or more steps such that the sample to be tested is contained in the lower well and a protective layer for protecting the sample, such as oil, is contained in the upper well, thereby preventing evaporation of the sample due to heating at the time of the biomaterial reaction, and thus, improving reliability in analysis.

    摘要翻译： 本发明提供一种用于确认或检测生物材料反应的生物反应装置芯片，更具体地，是生物反应装置芯片，其中在板中形成多个孔以容纳待测试的生物材料，从而同时分析各种靶 形成为具有两个以上的步骤的结构，使得待测试样品包含在下部井中，并且用于保护样品（例如油）的保护层被包含在上部井中，从而防止 在生物材料反应时由于加热而使样品蒸发，从而提高分析的可靠性。

    Semiconductor memory devices having separate read and write global data lines and associated methods
    7.
    发明申请
    Semiconductor memory devices having separate read and write global data lines and associated methods 失效
    半导体存储器件具有单独的读和写全局数据线和相关联的方法

    公开(公告)号：US20060023483A1

    公开(公告)日：2006-02-02

    申请号：US11186691

    申请日：2005-07-21

    申请人： Jae-Young Lee ,  Chi Kim ,  Sung-Min Seo

    发明人： Jae-Young Lee ,  Chi Kim ,  Sung-Min Seo

    IPC分类号： G11C5/02

    CPC分类号： G11C7/10 ,  G11C7/18

    摘要： Semiconductor memory devices include a memory cell array region having a plurality of memory cells, a local data I/O line pair that is electrically connected to the plurality of memory cells, a local sense amplifier that is electrically connected to the local data I/O line pair, a read global data I/O line pair that is electrically connected to the local sense amplifier and that is configured to transmit data during a read operation and a write global data I/O line pair that is electrically connected to the local sense amplifier that is configured to transmit data during a write operation.

    摘要翻译： 半导体存储器件包括具有多个存储器单元的存储单元阵列区域，电连接到多个存储单元的本地数据I / O线对，与本地数据I / O电连接的本地读出放大器 线对，读取的全局数据I / O线对，其被电连接到本地读出放大器，并且被配置为在读取操作期间传输数据，并且写入全局数据I / O线对被电连接到本地感测 配置为在写入操作期间传输数据的放大器。

    Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits
    8.
    发明申请
    Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits 有权
    缓冲电路和存储器系统，用于根据数据位数选择性地输出数据选通信号

    公开(公告)号：US20050111273A1

    公开(公告)日：2005-05-26

    申请号：US10884723

    申请日：2004-07-02

    申请人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

    发明人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

    IPC分类号： G11C7/00 ,  G11C5/00 ,  G11C7/10

    CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066

    摘要： Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits. When the number of processed data bits is n, the control signal is set to a first level and the inverted control signal is set to a second level, and when the number of processed data bits is k, the control signal is set to a second level and the inverted control signal is set to a first level. Since the buffer circuit and the memory system selectively output the data strobe signal according to the number of data bits, a point of time when the data are latched can be advanced and a setup/hold time of the data can be reduced.

    摘要翻译： 提供了一种用于根据数据位数选择性地输出数据选通信号的缓冲电路和存储系统。 缓冲电路包括第一缓冲单元，第二缓冲单元和第三缓冲单元。 第一缓冲器单元放大并输出第一信号。 第二缓冲器单元放大并输出第二信号，或者根据控制信号的逻辑电平输出第一信号。 第三缓冲器单元根据反相控制信号的逻辑电平放大第一信号以发送或不发送放大的第一信号到第二缓冲器单元。 控制信号和反相控制信号的逻辑电平根据处理的数据位的数量来确定。 当处理数据位数为n时，将控制信号设置为第一电平，将反相控制信号设置为第二电平，当处理数据位数为k时，将控制信号设置为第二电平 电平，并且反相控制信号被设置为第一电平。 由于缓冲电路和存储器系统根据数据位数选择性地输出数据选通信号，所以可以提前数据锁存的时间点，并且可以减少数据的建立/保持时间。

    Nanostructure sensors
    10.
    发明授权
    Nanostructure sensors 有权
    纳米结构传感器

    公开(公告)号：US08072226B2

    公开(公告)日：2011-12-06

    申请号：US11995916

    申请日：2007-08-06

    申请人： Young June Park ,  Jun Ho Cheon ,  Sung Min Seo

    发明人： Young June Park ,  Jun Ho Cheon ,  Sung Min Seo

    IPC分类号： G01R31/02

    CPC分类号： G01N27/127 ,  G01N27/4146

    摘要： Embodiments feature a sensor including a nanostructure and methods for manufacturing the same. In some embodiments, a sensor includes a substrate, a first electrode disposed on the substrate, and a second electrode disposed on the substrate. The second electrode is spaced apart from the first electrode and surrounding the first electrode. The sensor includes at least one nanostructure contacting the first electrode and the second electrode, in which the nanostructure is configured to vary an electrical characteristic according to an object to be sensed.

    摘要翻译： 实施例的特征在于包括纳米结构的传感器及其制造方法。 在一些实施例中，传感器包括衬底，设置在衬底上的第一电极和设置在衬底上的第二电极。 第二电极与第一电极间隔开并围绕第一电极。 传感器包括与第一电极和第二电极接触的至少一个纳米结构，其中纳米结构被配置成根据待感测的物体改变电特性。