公开(公告)号：US20080093723A1

公开(公告)日：2008-04-24

申请号：US11584383

申请日：2006-10-19

Applicant: Todd B. Myers ,  Chunho Kim ,  Seung Ae Lee ,  Suresh B. Yeruva

Inventor： Todd B. Myers ,  Chunho Kim ,  Seung Ae Lee ,  Suresh B. Yeruva

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A microelectronic assembly includes a first microelectronic device electrically coupled with a second microelectronic device via wire bond attachment, the first microelectronic device being structurally coupled with the second microelectronic device via a polymer adhesive, and one or more passive(s) coupled with the first microelectronic device wherein at least one or more passive(s) are enclosed in the polymer adhesive between the first and second microelectronic devices.

Abstract translation: 微电子组件包括通过引线键合附接与第二微电子器件电耦合的第一微电子器件，第一微电子器件通过聚合物粘合剂在结构上与第二微电子器件耦合，以及与第一微电子器件耦合的一个或多个无源器件 其中在第一和第二微电子器件之间的聚合物粘合剂中封入至少一个或多个无源器件。

公开(公告)号：US08952532B2

公开(公告)日：2015-02-10

申请号：US13893193

申请日：2013-05-13

Applicant: Tieyu Zheng ,  Sumit Kumar ,  Sridhar Nara ,  Renee D. Garcia ,  Manohar S. Konchady ,  Suresh B. Yeruva ,  Lynn H. Chen ,  Tyler N. Osborn ,  Sairam Agraharam

Inventor： Tieyu Zheng ,  Sumit Kumar ,  Sridhar Nara ,  Renee D. Garcia ,  Manohar S. Konchady ,  Suresh B. Yeruva ,  Lynn H. Chen ,  Tyler N. Osborn ,  Sairam Agraharam

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L24/81 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0603 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1413 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).

Abstract translation: 具有通过焊料互连的第一和第二衬底的集成电路（IC）封装堆栈还包括混合侧向尺寸的阻焊剂开口（SRO）在衬底的一个区域上空间变化。 在实施例中，SRO尺寸在至少两个不同直径之间变化，作为取决于衬底区域内的位置的衬底之间的估计间隙的函数。 在至少一个衬底中的偏转减小衬底之间的共形性的实施例中，通过在较小间隙的区域中相对于SRO尺寸的较大间隙的区域中减小SRO的横向尺寸，从固定体积的焊料提供变化的焊点高度 。 在实施例中，第一基板可以是IC芯片，封装基板或插入件中的任何一个，而第二基板可以是另一个IC芯片，封装基板，插入件或印刷电路板（PCB）中的任何一个。

公开(公告)号：US20140332956A1

公开(公告)日：2014-11-13

申请号：US13893193

申请日：2013-05-13

Applicant: Tieyu ZHENG ,  Sumit KUMAR ,  Sridhar NARA ,  Renee D. GARCIA ,  Manohar S. KONCHADY ,  Suresh B. YERUVA ,  Lynn H. CHEN ,  Tyler N. OSBORN ,  Sairam AGRAHARAM

Inventor： Tieyu ZHENG ,  Sumit KUMAR ,  Sridhar NARA ,  Renee D. GARCIA ,  Manohar S. KONCHADY ,  Suresh B. YERUVA ,  Lynn H. CHEN ,  Tyler N. OSBORN ,  Sairam AGRAHARAM

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/81 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0603 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1413 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).

Abstract translation: 具有通过焊料互连的第一和第二衬底的集成电路（IC）封装堆栈还包括混合侧向尺寸的阻焊剂开口（SRO）在衬底的一个区域上空间变化。 在实施例中，SRO尺寸在至少两个不同直径之间变化，作为取决于衬底区域内的位置的衬底之间的估计间隙的函数。 在至少一个衬底中的偏转减小衬底之间的共形性的实施例中，通过在较小间隙的区域中相对于SRO尺寸的较大间隙的区域中减小SRO的横向尺寸，从固定体积的焊料提供变化的焊点高度 。 在实施例中，第一基板可以是IC芯片，封装基板或插入件中的任何一个，而第二基板可以是另一个IC芯片，封装基板，插入件或印刷电路板（PCB）中的任何一个。