公开(公告)号：US08952532B2

公开(公告)日：2015-02-10

申请号：US13893193

申请日：2013-05-13

申请人： Tieyu Zheng ,  Sumit Kumar ,  Sridhar Nara ,  Renee D. Garcia ,  Manohar S. Konchady ,  Suresh B. Yeruva ,  Lynn H. Chen ,  Tyler N. Osborn ,  Sairam Agraharam

发明人： Tieyu Zheng ,  Sumit Kumar ,  Sridhar Nara ,  Renee D. Garcia ,  Manohar S. Konchady ,  Suresh B. Yeruva ,  Lynn H. Chen ,  Tyler N. Osborn ,  Sairam Agraharam

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/768

CPC分类号： H01L24/81 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0603 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1413 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

摘要： An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).

摘要翻译： 具有通过焊料互连的第一和第二衬底的集成电路（IC）封装堆栈还包括混合侧向尺寸的阻焊剂开口（SRO）在衬底的一个区域上空间变化。 在实施例中，SRO尺寸在至少两个不同直径之间变化，作为取决于衬底区域内的位置的衬底之间的估计间隙的函数。 在至少一个衬底中的偏转减小衬底之间的共形性的实施例中，通过在较小间隙的区域中相对于SRO尺寸的较大间隙的区域中减小SRO的横向尺寸，从固定体积的焊料提供变化的焊点高度 。 在实施例中，第一基板可以是IC芯片，封装基板或插入件中的任何一个，而第二基板可以是另一个IC芯片，封装基板，插入件或印刷电路板（PCB）中的任何一个。

公开(公告)号：US09704735B2

公开(公告)日：2017-07-11

申请号：US14463285

申请日：2014-08-19

申请人： Manohar S. Konchady ,  Tao Wu ,  Mihir K. Roy ,  Wei-Lun K. Jen ,  Yi Li

发明人： Manohar S. Konchady ,  Tao Wu ,  Mihir K. Roy ,  Wei-Lun K. Jen ,  Yi Li

IPC分类号： H01L21/683 ,  H01L23/538 ,  H01L23/498

CPC分类号： H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19106

摘要： A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

公开(公告)号：US08907461B1

公开(公告)日：2014-12-09

申请号：US13904169

申请日：2013-05-29

申请人： Manohar S. Konchady ,  Mihir K. Roy

发明人： Manohar S. Konchady ,  Mihir K. Roy

IPC分类号： H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L23/3677 ,  H01L23/38 ,  H01L23/42 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L27/16 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/00

摘要： The subject matter of the present application relates to a heat dissipation device that is embedded within a microelectronic die. The heat dissipation device may be fabricated by forming at least one trench extending into the microelectronic die from a microelectronic die back surface, which opposes an active surface thereof, and filling the trenches with at least one layer of thermally conductive material. In one embodiment, the heat dissipation device may be a thermoelectric cooling device.

摘要翻译： 本申请的主题涉及嵌入在微电子管芯内的散热装置。 散热装置可以通过形成从微电子管芯背表面延伸到微电子管芯中的至少一个沟槽来制造，所述微电子管芯背表面与其活性表面相对，并且用至少一层导热材料填充沟槽。 在一个实施例中，散热装置可以是热电冷却装置。

公开(公告)号：US20160056102A1

公开(公告)日：2016-02-25

申请号：US14463285

申请日：2014-08-19

申请人： Manohar S. Konchady ,  Tao Wu ,  Mihir K. Roy ,  Wei-Lun K. Jen ,  Yi Li

发明人： Manohar S. Konchady ,  Tao Wu ,  Mihir K. Roy ,  Wei-Lun K. Jen ,  Yi Li

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/535

CPC分类号： H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19106

摘要： A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

摘要翻译： 公开了一种具有双面阻焊层的无芯封装基板。 无芯封装衬底具有与顶侧相反的顶侧和底侧，并且包括由至少一个绝缘层，至少一个通孔和至少一个导电层形成的单个堆积结构。 无芯封装基板还包括底侧的底部多个接触焊盘和顶侧上的顶部多个接触焊盘。 底部阻焊层位于底侧，顶部阻焊层在顶侧。 双面阻焊剂的概念扩展到具有C4互连间距的互连桥的封装。