公开(公告)号：US20180158759A1

公开(公告)日：2018-06-07

申请号：US15883151

申请日：2018-01-30

Applicant: Infineon Technologies AG

Inventor： Georg MEYER-BERG

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24155 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1715 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00

Abstract: Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

公开(公告)号：US20170287861A1

公开(公告)日：2017-10-05

申请号：US15506956

申请日：2015-08-28

Applicant: NIPPON MICROMETAL CORPORATION ,  NIPPON STEEL & SUMIKIN MATERIALS CO., LTD.

Inventor： Takashi YAMADA ,  Daizo ODA ,  Teruo HAIBARA ,  Shinichi TERASHIMA

IPC: H01L23/00

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K2101/38 ,  B23K2101/42 ,  B23K2103/12 ,  C22C9/00 ,  H01L23/12 ,  H01L23/50 ,  H01L24/11 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647

Abstract: A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars.

公开(公告)号：US20170243842A1

公开(公告)日：2017-08-24

申请号：US15589027

申请日：2017-05-08

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jiun Yi WU ,  Hsueh-Lung CHENG ,  Shou-Yi WANG

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L24/03 ,  H01L21/76804 ,  H01L21/7685 ,  H01L21/76879 ,  H01L22/32 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/03416 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0392 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05091 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2924/01029 ,  H01L2924/20643 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

公开(公告)号：US09431366B2

公开(公告)日：2016-08-30

申请号：US14705005

申请日：2015-05-06

Applicant: International Business Machines Corporation

Inventor： Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/3494 ,  H01L21/4853 ,  H01L21/50 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/75252 ,  H01L2224/75272 ,  H01L2224/75283 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/0271 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/1316 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

Abstract translation: 一种形成3D封装的方法。 该方法可以包括通过施加第一选择性不均匀的热和第一均匀压力将插入件连接到具有第一多个焊料凸块的固态扩散的层压芯片载体; 通过施加第二选择性不均匀的热和第二均匀压力将第二多个焊料凸块的固态扩散连接到所述插入件的顶部芯片; 将所述第一和第二多个焊料凸起加热到大于所述第一和第二多个焊料凸块的回流温度的温度，其中所述第二多个焊料凸块在所述第一多个焊料凸点之前达到回流温度， 其中第一和第二选择性不均匀热分别小于第一和第二多个焊料凸块的回流温度。

公开(公告)号：US20160218077A1

公开(公告)日：2016-07-28

申请号：US15023702

申请日：2014-09-29

Applicant: LINTEC CORPORATION

Inventor： Yuichiro Azuma ,  Sayaka Tsuchiyama ,  Akio Kabuto

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/29 ,  B32B7/12 ,  B32B27/08 ,  B32B27/16 ,  B32B27/20 ,  B32B27/22 ,  B32B27/308 ,  B32B2250/44 ,  B32B2457/14 ,  C09J7/20 ,  C09J2201/36 ,  C09J2201/61 ,  C09J2203/326 ,  C09J2205/31 ,  H01L21/6836 ,  H01L23/295 ,  H01L23/3142 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/54486 ,  H01L2224/29083 ,  H01L2224/2919 ,  H01L2924/0002 ,  H01L2924/0635 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643

Abstract: The present invention relates to a composite sheet for resin film formation composed of a pressure-sensitive adhesive sheet having a pressure-sensitive adhesive layer on a base and a heat curable film for resin film formation provided on the pressure-sensitive adhesive layer. The film for resin film formation includes a binder component having a reactive double bond group. The pressure-sensitive adhesive layer includes a non-energy ray curable pressure-sensitive adhesive composition or a cured product of an energy ray curable pressure-sensitive adhesive composition.

Abstract translation: 本发明涉及一种用于树脂膜形成的复合片材，其由在基底上具有压敏粘合剂层的压敏粘合片和用于树脂膜形成的热固化膜组成，该粘合片材设置在压敏粘合剂层上。 用于树脂膜形成的膜包括具有反应性双键基团的粘合剂组分。 压敏粘合剂层包括非能量射线固化型压敏粘合剂组合物或能量射线固化型压敏粘合剂组合物的固化产物。

公开(公告)号：US20160190044A1

公开(公告)日：2016-06-30

申请号：US14827361

申请日：2015-08-17

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24155 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1715 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00

Abstract: Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.

Abstract translation: 各种实施例提供了由载体上的层构成的芯片封装，在该层上的另外的载体材料，其中移除其它载体材料的一个或多个部分以及具有一个或多个接触焊盘的芯片，其中芯片被粘附 通过层到载体。 还提供了由多个芯片组成的晶片级封装，所述芯片通过从所述另外的载体材料释放的所述层的多个部分粘附到所述载体。

公开(公告)号：US09266196B2

公开(公告)日：2016-02-23

申请号：US14613256

申请日：2015-02-03

Applicant: Senju Metal Industry Co., Ltd.

Inventor： Takashi Akagawa ,  Hiroyoshi Kawasaki ,  Kazuhiko Matsui ,  Yuichi Koikeda ,  Masaru Sasaki ,  Hiroyuki Yamasaki ,  Takahiro Roppongi ,  Daisuke Soma ,  Isamu Sato

IPC: H01B5/00 ,  H01L23/48 ,  B32B15/04 ,  B23K35/02 ,  B23K35/00 ,  C22C5/06 ,  B23K35/30 ,  H01B1/02 ,  H01L23/00 ,  C22C19/03 ,  C22C19/07

CPC classification number: B23K35/025 ,  B22F1/0062 ,  B22F1/0074 ,  B22F1/02 ,  B23K35/00 ,  B23K35/0244 ,  B23K35/3006 ,  B23K35/3033 ,  B23K35/3046 ,  C22C5/06 ,  C22C13/00 ,  C22C19/03 ,  C22C19/07 ,  H01B1/02 ,  H01L24/13 ,  H01L2224/13014 ,  H01L2224/13139 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0109 ,  H01L2924/01092 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065

Abstract: Providing an Ag ball having a low alpha dose and a high sphericity regardless of impurity elements having an amount equal to or more than a predetermined value except for Ag. In order to suppress a soft error and reduce an connection fault, a content of U is equal to or less than 5 ppb, a content of Th is equal to or less than 5 ppb, a purity is equal to or more than 99.9% but equal to or less than 99.9995%, an alpha dose is equal to or less than 0.0200 cph/cm2, a content of either Pb or Bi or a total content of both Pb and Bi is equal to or more than 1 ppm, and a sphericity is equal to or more than 0.90.

Abstract translation: 提供具有低α剂量和高球形度的Ag球，而不管除了Ag之外具有等于或大于预定值的量的杂质元素。 为了抑制软错误并减少连接故障，U的含量等于或小于5ppb，Th的含量等于或小于5ppb，纯度等于或大于99.9％，但是 等于或小于99.9995％，α剂量等于或小于0.0200cph / cm 2，Pb或Bi的含量或Pb和Bi的总含量等于或大于1ppm，并且球形度 等于或大于0.90。

公开(公告)号：US20140217570A1

公开(公告)日：2014-08-07

申请号：US14158690

申请日：2014-01-17

Applicant: SCHOTT AG

Inventor： Robert Hettler ,  Kenneth Tan ,  Georg Mittermeyer ,  Karsten Droegemueller

IPC: H01L23/10 ,  H01L23/08 ,  H01L23/66

CPC classification number: H01L23/08 ,  H01L23/045 ,  H01L23/3157 ,  H01L23/64 ,  H01L23/66 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6622 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/2065 ,  H01L2924/20649 ,  H01L2924/20645 ,  H01L2924/20644 ,  H01L2924/20643 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A transistor outline housing is provided that has bonding wires on an upper surface. The bonding wires are reduced in length and have connection leads with an excess length at an end opposite the bonding end.

Abstract translation: 提供了在上表面具有接合线的晶体管轮廓外壳。 接合线的长度减小，并且在与接合端相对的端部处具有连续引线，其具有多余的长度。

公开(公告)号：US07095293B2

公开(公告)日：2006-08-22

申请号：US10711306

申请日：2004-09-09

Applicant: Kenneth V. Buer

Inventor： Kenneth V. Buer

IPC: H03H7/38

CPC classification number: H01L24/06 ,  H01L23/50 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/665 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F3/195 ,  H03F2200/12 ,  H01L2924/00014 ,  H01L2924/20643 ,  H01L2924/20653 ,  H01L2924/20654 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

Abstract: In general, the present invention provides an RF signal amplification system having an improved layout. The size of the MMIC can be reduced without loss of functionality and/or additional functionality can be added to the MMIC without increasing the size of the MMIC. The MMIC is configured with an off-chip bias feed system. The MMIC is configured with landing zones for receiving a bond wire such that on-chip bias circuitry can be reduced and/or eliminated.

Abstract translation: 通常，本发明提供了一种具有改进布局的RF信号放大系统。 可以减少MMIC的尺寸而不损失功能，并且/或者可以在不增加MMIC的尺寸的情况下将附加功能添加到MMIC。 MMIC配置了片外偏置馈电系统。 MMIC配置有用于接收接合线的着陆区，使得可以减少和/或消除片上偏置电路。

公开(公告)号：US09911705B2

公开(公告)日：2018-03-06

申请号：US15456746

申请日：2017-03-13

Applicant: Mitsubishi Electric Corporation

Inventor： Yosuke Nakata ,  Masayoshi Tarutani

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L23/498 ,  H01L24/01 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/034 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/07025 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01201 ,  H01L2924/01014

Abstract: A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder.