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    VIDEO STORING METHOD AND DEVICE BASED ON VARIABLE BIT ALLOCATION AND RELATED VIDEO ENCODING AND DECODING APPARATUSES
    2.
    发明申请
    VIDEO STORING METHOD AND DEVICE BASED ON VARIABLE BIT ALLOCATION AND RELATED VIDEO ENCODING AND DECODING APPARATUSES 审中-公开
    基于可变位分配和相关视频编码和解码设备的视频存储方法和设备

    公开(公告)号：US20110249959A1

    公开(公告)日：2011-10-13

    申请号：US13082937

    申请日：2011-04-08

    申请人： Dong-Sun KIM ,  SeungYerl LEE ,  Tae-Ho HWANG ,  Byung-Ho CHOI

    发明人： Dong-Sun KIM ,  SeungYerl LEE ,  Tae-Ho HWANG ,  Byung-Ho CHOI

    IPC分类号： H04N5/919

    CPC分类号： H04N9/8042 ,  H04N19/119 ,  H04N19/149 ,  H04N19/176 ,  H04N19/428

    摘要： Provided are a method and device for storing video on the basis of a variable bit allocation to variably control a buffer size. Also provided are video encoding and decoding apparatuses using the same. The device divides a video image to be stored into a plurality of first basic blocks, checks pixel values of second basic blocks for each of the divided first basic blocks, and allocates bits to each of the first basic blocks according to a difference between maximum and minimum values of the checked pixel values. Also, the device compresses and stores pixel information about the first basic block in the allocated bits, and then de-compresses the compressed pixel information according to the maximum and minimum values for each of the first basic blocks.

    摘要翻译： 提供了一种用于基于可变位分配来存储视频以便可变地控制缓冲器大小的方法和装置。 还提供了使用其的视频编码和解码装置。 该设备将要存储的视频图像划分为多个第一基本块，检查每个划分的第一基本块的第二基本块的像素值，并且根据最大和最大基本块之间的差分配每个第一基本块的位 检查的像素值的最小值。 此外，设备在分配的比特中压缩并存储关于第一基本块的像素信息，然后根据每个第一基本块的最大值和最小值来解压缩压缩像素信息。

    APPARATUS OF DIGITAL MAC FOR IEEE 802.15.4 SYSTEM AND SYSTEM THEREOF
    3.
    发明申请
    APPARATUS OF DIGITAL MAC FOR IEEE 802.15.4 SYSTEM AND SYSTEM THEREOF 审中-公开
    用于IEEE 802.15.4系统及其系统的数字MAC的设备

    公开(公告)号：US20100057958A1

    公开(公告)日：2010-03-04

    申请号：US12200439

    申请日：2008-08-28

    申请人： Dong Sun Kim ,  Tae Ho Hwang ,  Yeon Kug Moon ,  Kwang Ho Won

    发明人： Dong Sun Kim ,  Tae Ho Hwang ,  Yeon Kug Moon ,  Kwang Ho Won

    IPC分类号： G06F13/42

    CPC分类号： H04W99/00 ,  H04W74/00 ,  H04W84/10

    摘要： There is provided a digital MAC apparatus for an IEEE 802.15.4 based communication system, which is implemented in hardware. The digital MAC apparatus having a processor of a Wireless Personal Area Network (WPAN) communication system and a data bus transferring data includes a frame generating unit generating and outputting a frame on the basis of input data; a frame parsing unit parsing an input frame input through the data bus, and generating and outputting a control signal or transmission and receipt data; and a controller operating at least one of the frame generating unit and the frame parsing unit according to the generated control signal, and communicating the output frame or data with the processor according to the operation.

    摘要翻译： 提供了一种用于基于IEEE 802.15.4的通信系统的数字MAC设备，其以硬件实现。 具有无线个域网（WPAN）通信系统的处理器和数据总线传送数据的数字MAC设备包括：帧生成单元，基于输入数据生成并输出帧; 帧解析单元解析通过数据总线输入的输入帧，并且生成并输出控制信号或发送和接收数据; 以及根据生成的控制信号来操作帧生成单元和帧解析单元中的至少一个的控制器，并且根据该操作与输入帧或数据与处理器通信。

    SMALL LOW POWER EMBEDDED SYSTEM AND PREEMPTION AVOIDANCE METHOD THEREOF
    4.
    发明申请
    SMALL LOW POWER EMBEDDED SYSTEM AND PREEMPTION AVOIDANCE METHOD THEREOF 审中-公开
    小功率嵌入式系统及其避免方法

    公开(公告)号：US20090172684A1

    公开(公告)日：2009-07-02

    申请号：US12193875

    申请日：2008-08-19

    申请人： Tae Ho HWANG ,  Yeon Kug MOON ,  Dong Sun KIM ,  Kwang Ho WON

    发明人： Tae Ho HWANG ,  Yeon Kug MOON ,  Dong Sun KIM ,  Kwang Ho WON

    IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F1/04

    CPC分类号： G06F13/24 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/4887 ,  Y02D10/24

    摘要： Provided are a small low power embedded system and a preemption avoidance method thereof. A method for avoiding preemption in a small low power embedded system includes fetching and running a periodic atomic task from a periodic run queue, reducing any one of periodic atomic tasks or performing the change of a task after changing a field of the run periodic atomic task into a run standby state, according to a result value of the run of the periodic atomic task, fetching a sporadic atomic task from a sporadic run queue, and acquiring a system clock, running the fetched sporadic atomic task according to run time in the worst condition, and reducing any one of sporadic atomic tasks or performing the change of an event after a field of the run sporadic atomic task into a run standby state, according to a result value of the run of the sporadic atomic task.

    摘要翻译： 提供了一种小型低功率嵌入式系统及其抢占避免方法。 一种在小型低功率嵌入式系统中避免抢占的方法包括从周期性运行队列中取出和运行周期性原子任务，减少任何一个周期性原子任务，或者在改变运行周期性原子任务的一个字段之后执行任务改变 根据周期性原子任务运行的结果值，从零星运行队列中获取零星原子任务，并获取系统时钟，根据运行时间最差运行获取的零星原子任务，进入运行待机状态 条件，并且根据零星原子任务的运行的结果值，减少零星原子任务中的任何一个或者在运行零星原子任务的字段之后的事件的更改进入运行备用状态。

    Decoding device for context-based adaptive binary arithmetic coding (CABAC) technique
    6.
    发明授权
    Decoding device for context-based adaptive binary arithmetic coding (CABAC) technique 有权
    用于基于上下文的自适应二进制算术编码（CABAC）技术的解码装置

    公开(公告)号：US08319672B2

    公开(公告)日：2012-11-27

    申请号：US13083063

    申请日：2011-04-08

    申请人： Dong-Sun Kim ,  SeungYerl Lee ,  Tae-Ho Hwang ,  Byung-Ho Choi

    发明人： Dong-Sun Kim ,  SeungYerl Lee ,  Tae-Ho Hwang ,  Byung-Ho Choi

    IPC分类号： H03M7/00

    CPC分类号： H03M7/4018

    摘要： A decoding device is suitable for a context-based adaptive binary arithmetic coding (CABAC) technique and allows a real-time decoding of high-definition video. The CABAC decoding device allows a simultaneous performing since determination according to multiple conditions is based on logic circuits when the device is formed in hardware. Additionally, when one macro block starts to be decoded, the device reads and stores information about neighboring macro blocks at a time from a memory. Therefore, the device does not need to access the memory at every operation and this improves the overall decoding speed.

    摘要翻译： 解码装置适用于基于上下文的自适应二进制算术编码（CABAC）技术，并允许高清视频的实时解码。 CABAC解码装置允许同时执行，因为当硬件形成装置时，根据多个条件的确定是基于逻辑电路。 此外，当一个宏块开始解码时，设备一次从存储器读取和存储关于相邻宏块的信息。 因此，在每次操作时，设备不需要访问存储器，这提高了整体解码速度。

    Hardwired scheduler for low power wireless device processor and method for using the same
    8.
    发明申请
    Hardwired scheduler for low power wireless device processor and method for using the same 审中-公开
    用于低功耗无线设备处理器的硬连线调度器及其使用方法

    公开(公告)号：US20070157207A1

    公开(公告)日：2007-07-05

    申请号：US11474417

    申请日：2006-06-26

    申请人： Yong-Ho Kim ,  Byoung-Chul Song ,  Tae-Ho Hwang ,  Seong-Dong Kim ,  We-Duke Cho

    发明人： Yong-Ho Kim ,  Byoung-Chul Song ,  Tae-Ho Hwang ,  Seong-Dong Kim ,  We-Duke Cho

    IPC分类号： G06F9/46

    CPC分类号： G06F9/485 ,  G06F9/4893 ,  Y02D10/24

    摘要： The present invention relates to a hardwired scheduler for low power wireless device processor and a method for using the same wherein, for a processor used in a sensor node, ubiquitous small node and a wireless communication device which require a low power consumption, a storage of the currently running process and the process to be executed in priority in a list of subsequent processes to be carried out are automatically transmitted to the processor core, and the number of oscillations of the clock generator which operates the processor core is adjusted to be suitable for each process to reduce the power consumed by the processor to be applicable to devices operating on a network which require a low power consumption and small delay time.

    摘要翻译： 本发明涉及一种用于低功率无线设备处理器的硬接线调度器及其使用方法，其中，对于在传感器节点中使用的处理器，普遍存在的小节点和需要低功耗的无线通信设备，存储 当前运行的处理和要执行的后续处理的列表中优先执行的处理被自动发送到处理器核心，并且调整操作处理器核心的时钟发生器的振荡次数以适合于 每个过程减少处理器消耗的功率，以适用于需要低功耗和小延迟时间的网络上运行的设备。

    Apparatus and method for controlling operation state of physical layer
    9.
    发明授权
    Apparatus and method for controlling operation state of physical layer 有权
    控制物理层运行状态的装置和方法

    公开(公告)号：US08693395B2

    公开(公告)日：2014-04-08

    申请号：US12648832

    申请日：2009-12-29

    申请人： Tae Ho Hwang ,  Dong Sun Kim ,  Kwang-Ho Won

    发明人： Tae Ho Hwang ,  Dong Sun Kim ,  Kwang-Ho Won

    IPC分类号： H04W4/00 ,  H04B3/36 ,  H04B1/38

    CPC分类号： H04L1/188

    摘要： An apparatus for controlling IEEE 802.15.4 physical layer operation state is provided. The physical layer operation state controlling apparatus defines an operation state of a physical layer including a Hardwired Low-MAC (HL-MAC) device in which functions of IEEE 802.15.4 MAC layer are hardwired, and includes a state module for controlling the operation state of the physical layer. The state module includes a Finite State Machine (FSM) for, when receiving an event for the operation state of the physical layer, transiting to a state module corresponding to the event and controlling the operation state of the physical layer; and an interrupt handler for converting an interrupt received from the physical layer to the event corresponding to a register of the state module and sending the event to the FSM. Hence, by means of the state machine for the IEEE 802.15.4 PHY, the IEEE 802.15.4 physical layer operation state can be controlled to optimize the operations of the upper MAC.

    摘要翻译： 提供了一种用于控制IEEE 802.15.4物理层操作状态的装置。 物理层操作状态控制装置定义包括其中IEEE 802.15.4 MAC层的功能是硬连线的硬连线低MAC（HL-MAC）设备的物理层的操作状态，并且包括用于控制操作状态的状态模块 的物理层。 所述状态模块包括有限状态机（FSM），用于当接收到所述物理层的操作状态的事件时，转移到与所述事件相对应的状态模块并控制所述物理层的操作状态; 以及用于将从物理层接收的中断转换为与状态模块的寄存器相对应的事件并将事件发送到FSM的中断处理程序。 因此，通过IEEE 802.15.4 PHY的状态机，可以控制IEEE 802.15.4物理层操作状态，以优化上MAC的操作。

    DECODING DEVICE FOR CONTEXT-BASED ADAPTIVE BINARY ARITHMETIC CODING (CABAC) TECHNIQUE
    10.
    发明申请
    DECODING DEVICE FOR CONTEXT-BASED ADAPTIVE BINARY ARITHMETIC CODING (CABAC) TECHNIQUE 有权
    用于基于上下文的自适应二进制算术编码（CABAC）技术的解码设备

    公开(公告)号：US20110248871A1

    公开(公告)日：2011-10-13

    申请号：US13083063

    申请日：2011-04-08

    申请人： Dong-Sun KIM ,  SeungYerl LEE ,  Tae-Ho HWANG ,  Byung-Ho CHOI

    发明人： Dong-Sun KIM ,  SeungYerl LEE ,  Tae-Ho HWANG ,  Byung-Ho CHOI

    IPC分类号： H03M7/34

    CPC分类号： H03M7/4018

    摘要： A decoding device is suitable for a context-based adaptive binary arithmetic coding (CABAC) technique and allows a real-time decoding of high-definition video. The CABAC decoding device allows a simultaneous performing since determination according to multiple conditions is based on logic circuits when the device is formed in hardware. Additionally, when one macro block starts to be decoded, the device reads and stores information about neighboring macro blocks at a time from a memory. Therefore, the device does not need to access the memory at every operation and this improves the overall decoding speed.

    摘要翻译： 解码装置适用于基于上下文的自适应二进制算术编码（CABAC）技术，并允许高清视频的实时解码。 CABAC解码装置允许同时执行，因为当硬件形成装置时，根据多个条件的确定是基于逻辑电路。 此外，当一个宏块开始解码时，设备一次从存储器读取和存储关于相邻宏块的信息。 因此，在每次操作时，设备不需要访问存储器，这提高了整体解码速度。