公开(公告)号：US5815253A

公开(公告)日：1998-09-29

申请号：US760511

申请日：1996-12-05

Applicant: Jin-Sung Kim ,  Taek-Jin Lim ,  Gui-Jin Kim

Inventor： Jin-Sung Kim ,  Taek-Jin Lim ,  Gui-Jin Kim

IPC: G01N23/225 ,  F16L55/00 ,  F17D5/00 ,  G01N21/88 ,  G01N21/93 ,  G01N21/954 ,  G01N23/227 ,  G01N37/00 ,  G01Q60/24

CPC classification number: G01N21/88

Abstract: Method and apparatus for estimating the performance of a gas tube. The method comprising the steps of: (a) preparing a sample tube to be analyzed and cutting the sample tube in a desired size and shape; (b) examining distribution of defects and surface condition of the cut sample tube with an optical microscope; (c) analyzing structure and composition of surface defects which can not be measured in the step (b), to determine type and composition of the surface defects and shape of a surface grain; (d) analyzing structure of an inner surface-treated layer of the sample tube along the thickness thereof; and (e) synthetically analyzing data for defect density and surface roughness, which are numerically expressed through the steps (a) to (d), to define a reference data which can be used in a semiconductor manufacturing process.

Abstract translation: 用于估计气体管的性能的方法和装置。 该方法包括以下步骤：（a）准备要分析的样品管并以期望的尺寸和形状切割样品管; （b）用光学显微镜检查切割的样品管的缺陷和表面状况的分布; （c）分析在步骤（b）中不能测量的表面缺陷的结构和组成，以确定表面缺陷的形式和组成以及表面颗粒的形状; （d）沿其厚度分析样品管的内表面处理层的结构; 和（e）综合分析通过步骤（a）至（d）数值表示的缺陷密度和表面粗糙度的数据，以定义可用于半导体制造工艺的参考数据。

公开(公告)号：US20070152168A1

公开(公告)日：2007-07-05

申请号：US11617159

申请日：2006-12-28

Applicant: Taek-Jin Lim ,  Jin-Sung Kim ,  Sang-Ick Lee

Inventor： Taek-Jin Lim ,  Jin-Sung Kim ,  Sang-Ick Lee

IPC: G21G5/00

CPC classification number: G01N1/32 ,  G01N1/286

Abstract: In a substrate protecting member and a method of forming an analysis sample using the same, the substrate protecting member includes a protective layer attached to a semiconductor substrate to protect a defect portion of the semiconductor substrate and a sensing line including first, second and third conductive lines located on the protective layer. The first conductive line extends in a first direction. The second conductive line extends to an edge of the protective layer in a second direction different from the first direction. The second and third conductive lines are electrically connected to first and second end portions of the first conductive line, respectively. The third conductive line extends to an edge of the protective layer in the second direction.

Abstract translation: 在基板保护部件和使用其的分析用样品的形成方法中，基板保护部件包括附着于半导体基板的保护层，以保护半导体基板的缺陷部分，以及包括第一，第二和第三导电 位于保护层上的线。 第一导线沿第一方向延伸。 第二导线沿与第一方向不同的第二方向延伸到保护层的边缘。 第二和第三导线分别电连接到第一导电线的第一和第二端部。 第三导线在第二方向延伸到保护层的边缘。

公开(公告)号：US20090108323A1

公开(公告)日：2009-04-30

申请号：US12228772

申请日：2008-08-15

Applicant: Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

Inventor： Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

IPC: H01L29/788 ,  H01L21/3215 ,  H01L21/22

CPC classification number: H01L29/42324 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract translation: 提供一种制造非易失性存储器件的方法。 该方法包括形成在衬底上限定有源区的隔离图案，在有源区上形成浮置栅极图案，以及在浮栅图案上形成栅极线。 浮置栅极图案在有源区域上是自对准的，并且当浮栅图案更靠近有源区域时，其杂质离子浓度变得相对较低。

公开(公告)号：US5889282A

公开(公告)日：1999-03-30

申请号：US919154

申请日：1997-08-28

Applicant: Hee Seok Yang ,  Taek Jin Lim ,  Jae Sung Han

Inventor： Hee Seok Yang ,  Taek Jin Lim ,  Jae Sung Han

IPC: H01L21/66 ,  G01N23/227 ,  G01Q30/00 ,  H01J37/256 ,  H01J37/00

CPC classification number: G01N23/2276 ,  H01J2237/2511

Abstract: A method of Auger Electron Spectroscopic (AES) analysis for a surface of an insulating sample. The method is characterized by performing an AES analysis after depositing a conductive layer of a designated thickness on the surface of a sample containing an insulating layer by means of an ion beam sputtering for the purpose of the preventing charge accumulation. The conductive layer preferably is deposited to have a thickness of at least 6 .ANG. to 50 .ANG. and a beam voltage used for applying the conductive layer is at least 3 Kev. The conductive layer is made of any of iridium(Ir), chrome(Cr) and gold(Au). Because any electron charge generated on the sample is discharged via the conductive layer, the AES analysis can be performed for a sample containing an insulating layer.

Abstract translation: 绝缘样品表面的俄歇电子能谱（AES）分析方法。 该方法的特征在于，为了防止电荷累积，通过离子束溅射，在含有绝缘层的样品的表面上沉积指定厚度的导电层之后进行AES分析。 导电层优选沉积为具有至少6安培至50埃的厚度，并且用于施加导电层的束电压为至少3Kev。 导电层由铱（Ir），铬（Cr）和金（Au）中的任一种制成。 因为在样品上产生的任何电子电荷通过导电层放电，所以可以对含有绝缘层的样品进行AES分析。

公开(公告)号：US08497545B2

公开(公告)日：2013-07-30

申请号：US12986763

申请日：2011-01-07

Applicant: Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

Inventor： Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

IPC: H01L27/108

CPC classification number: H01L29/42324 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

公开(公告)号：US20110101437A1

公开(公告)日：2011-05-05

申请号：US12986763

申请日：2011-01-07

Applicant: Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

Inventor： Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract translation: 提供一种制造非易失性存储器件的方法。 该方法包括形成在衬底上限定有源区的隔离图案，在有源区上形成浮置栅极图案，以及在浮栅图案上形成栅极线。 浮置栅极图案在有源区域上是自对准的，并且当浮栅图案更靠近有源区域时，其杂质离子浓度变得相对较低。

公开(公告)号：US07888204B2

公开(公告)日：2011-02-15

申请号：US12228772

申请日：2008-08-15

Applicant: Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

Inventor： Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

IPC: H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract translation: 提供一种制造非易失性存储器件的方法。 该方法包括形成在衬底上限定有源区的隔离图案，在有源区上形成浮置栅极图案，以及在浮栅图案上形成栅极线。 浮置栅极图案在有源区域上是自对准的，并且当浮栅图案更靠近有源区域时，其杂质离子浓度变得相对较低。

公开(公告)号：US20070172977A1

公开(公告)日：2007-07-26

申请号：US11728869

申请日：2007-03-27

Applicant: Taek-jin Lim

Inventor： Taek-jin Lim

IPC: H01L21/00

CPC classification number: B24B37/042 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

Abstract translation: 半导体器件包括与器件特征对准的对准标记。 半导体器件包括器件特征，一对第一对准标记，一对第二对准标记和一对第三对准标记。 第一对准标记沿着第一方向与装置特征对准，并且邻近装置特征的相对侧。 第二对准标记沿着第二方向对准，其中装置特征基本上垂直于第一方向，并且与装置特征的相对侧相邻。 所述第三对准标记与所述第一方向上的所述第一对准标记对准，并且邻近所述装置特征的相对侧，其中所述第三标记位于所述第一对准标记和所述装置特征之间，并且所述第三标记中的每一个具有较短的长度 沿着第一方向比第一对准标记中的每一个。

公开(公告)号：US07211460B2

公开(公告)日：2007-05-01

申请号：US10960660

申请日：2004-10-07

Applicant: Taek-jin Lim

Inventor： Taek-jin Lim

IPC: H01L21/00

CPC classification number: B24B37/042 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

Abstract translation: 半导体器件包括与器件特征对准的对准标记。 半导体器件包括器件特征，一对第一对准标记，一对第二对准标记和一对第三对准标记。 第一对准标记沿着第一方向与装置特征对准，并且邻近装置特征的相对侧。 第二对准标记沿着第二方向对准，其中装置特征基本上垂直于第一方向，并且与装置特征的相对侧相邻。 所述第三对准标记与所述第一方向上的所述第一对准标记对准，并且邻近所述装置特征的相对侧，其中所述第三标记位于所述第一对准标记和所述装置特征之间，并且所述第三标记中的每一个具有较短的长度 沿着第一方向比第一对准标记中的每一个。

公开(公告)号：US20050079689A1

公开(公告)日：2005-04-14

申请号：US10960660

申请日：2004-10-07

Applicant: Taek-jin Lim

Inventor： Taek-jin Lim

IPC: H01L21/66 ,  B24B37/04 ,  H01L21/36 ,  H01L23/544

CPC classification number: B24B37/042 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

Abstract translation: 半导体器件包括与器件特征对准的对准标记。 半导体器件包括器件特征，一对第一对准标记，一对第二对准标记和一对第三对准标记。 第一对准标记沿着第一方向与装置特征对准，并且邻近装置特征的相对侧。 第二对准标记沿着第二方向对准，其中装置特征基本上垂直于第一方向，并且与装置特征的相对侧相邻。 所述第三对准标记与所述第一方向上的所述第一对准标记对准，并且邻近所述装置特征的相对侧，其中所述第三标记位于所述第一对准标记和所述装置特征之间，并且所述第三标记中的每一个具有较短的长度 沿着第一方向比第一对准标记中的每一个。