公开(公告)号：US5691568A

公开(公告)日：1997-11-25

申请号：US656033

申请日：1996-05-31

申请人： Tai-Yu Chou ,  Sanjay Dandia

发明人： Tai-Yu Chou ,  Sanjay Dandia

IPC分类号： H01L23/12 ,  H01L23/498 ,  H01L23/52 ,  H01L23/48

CPC分类号： H01L24/49 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48235 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： A semiconductor device package for one or more semiconductor dice having core circuits and input-output circuits uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the package substrate top surface and bottom surface. The top surface has lands connected to the conductive planes and to the power bond pads for the core circuits and input-output circuits on the semiconductor die. The top surface has many top traces connected to the signal bond pads on the semiconductor die. The package substrate may have a die paddle connected to one land and/or thermal vias to conduct heat away from the semiconductor die. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.

摘要翻译： 用于具有核心电路和输入 - 输出电路的一个或多个半导体晶片的半导体器件封装使用具有一对双平面导电平面和另一对双平面导电平面的封装衬底。 这对平面位于封装衬底顶表面和底表面之间的共面关系中。 顶表面具有连接到导电平面和用于半导体管芯上的核心电路和输入 - 输出电路的功率接合焊盘的焊盘。 顶表面具有连接到半导体管芯上的信号接合焊盘的许多顶部迹线。 封装衬底可以具有连接到一个焊盘和/或热通孔的管芯焊盘，以将热量从半导体管芯导出。 可以通过一对平面向芯片电路提供功率，并通过另一对平面对输入输出电路进行芯片去耦，从而使核心电路与输入 - 输出电路分离并最小化两组电路中的噪声导致的错开关。 核心电路和输入 - 输出电路可以由相同的电源或单独的电源供电。

公开(公告)号：US20110077562A1

公开(公告)日：2011-03-31

申请号：US12659042

申请日：2010-02-24

申请人： Fu-cheng Wang ,  Chung-Huang Yu ,  Nai-Chung Chang ,  Tai-yu Chou

发明人： Fu-cheng Wang ,  Chung-Huang Yu ,  Nai-Chung Chang ,  Tai-yu Chou

IPC分类号： A61H1/00

CPC分类号： A61H1/0266 ,  A61H3/00 ,  A61H2201/5007

摘要： The invention discloses a gait training device for people with walking disability. Using motors and six-bar linkage mechanism, the invention can guide users' ankles to follow preferred gait trajectories, and thus help people with walking disability practice correct gaits.

摘要翻译： 本发明公开了一种步行障碍者的步态训练装置。 使用电机和六杆联动机构，本发明可以指导用户的脚踝跟随优先步态，从而帮助行走障碍者练习正确的步态。

公开(公告)号：US5672911A

公开(公告)日：1997-09-30

申请号：US655599

申请日：1996-05-30

申请人： Sadanand R. Patil ,  Tai-Yu Chou ,  Prabhansu Chakrabarti

发明人： Sadanand R. Patil ,  Tai-Yu Chou ,  Prabhansu Chakrabarti

IPC分类号： H01L23/12 ,  H01L23/64 ,  H01L23/52 ,  H01L23/48

CPC分类号： H01L23/642 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/8547 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011

摘要： A semiconductor device package for one or more semiconductor dice uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the top traces and the bottom traces. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.

摘要翻译： 用于一个或多个半导体晶片的半导体器件封装使用具有一对双平面导电平面和另一对双平面导电平面的封装衬底。 这些平面对被定位在顶部迹线和底部迹线之间的共面关系中。 可以通过一对平面向芯片电路提供功率，并通过另一对平面对输入输出电路进行芯片去耦，从而使核心电路与输入 - 输出电路分离并最小化两组电路中的噪声导致的错开关。 核心电路和输入 - 输出电路可以由相同的电源或单独的电源供电。

公开(公告)号：US06519747B2

公开(公告)日：2003-02-11

申请号：US09837923

申请日：2001-04-18

申请人： Satyanarayana Nishtala ,  Jayarama N. Shenoy ,  Tai-Yu Chou ,  Michael C. Freda

发明人： Satyanarayana Nishtala ,  Jayarama N. Shenoy ,  Tai-Yu Chou ,  Michael C. Freda

IPC分类号： G06F945

CPC分类号： G06F17/5077 ,  G06F17/5031

摘要： One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of signal timings for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.

摘要翻译： 本发明的一个实施例提供了一种用于定义集成电路装置的信号定时的系统。 该系统通过首先为集成电路设备创建虚拟定时参考平面来操作。 然后，第一信号线从集成电路封装内的半导体管芯路由到集成电路封装的第一外部连接。 接下来，系统从第一外部连接到虚拟定时参考平面生成用于印刷电路板上的第一电路迹线的第一逃逸模式。 该第一逃逸模式指定从第一外部连接到印刷电路板到虚拟定时参考平面的路线。 最后，该系统为虚拟定时参考平面上的第一信号线和第一电路迹线的组合建立第一组信号定时。

公开(公告)号：US5825084A

公开(公告)日：1998-10-20

申请号：US795478

申请日：1997-02-11

申请人： John H. Lau ,  Yung Shih Chen ,  Tai-Yu Chou ,  Frank H. Wu ,  Kuan Luen Chen ,  Wei H. Koh

发明人： John H. Lau ,  Yung Shih Chen ,  Tai-Yu Chou ,  Frank H. Wu ,  Kuan Luen Chen ,  Wei H. Koh

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01L23/12 ,  H01L23/28

CPC分类号： H01L23/49805 ,  H01L23/4985 ,  H01L23/50 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15747

摘要： The present invention discloses a new substrate with two metal layer circuit structure and layout for semiconductor packaging. The speed and performance characteristics of the semiconductor device are optimized while the packaging structure is simplified by utilizing only one dielectric layer and conventional printed circuit board fabrication process. The difficulties encountered due to the complexities and higher cost of production required for the multiple layer and high density configuration are thus avoided. The improved circuit structure is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide inter-layer connections. In addition to the benefits of high performance, low cost, the improved circuit structure and package layout provide flexibility allowing higher degree of freedom for selecting the location and number of input and output signal lines and connections to the ground and power planes from the semiconductor device.

摘要翻译： 本发明公开了一种具有两个金属层电路结构和半导体封装布局的新基片。 通过仅使用一个电介质层和传统的印刷电路板制造工艺简化了封装结构，优化了半导体器件的速度和性能特性。 因此避免了由于多层和高密度构造所需的复杂性和更高的生产成本而遇到的困难。 改进的电路结构通过在衬底的一侧上实现分段环并在另一侧上实现分裂平面来实现，从而形成单层衬底结构。 衬底的边缘涂有金属层以提供层间连接。 除了高性能，低成本的优点之外，改进的电路结构和封装布局提供了灵活性，允许更高的自由度来选择输入和输出信号线的位置和数量以及从半导体器件到地面和电源平面的连接 。