公开(公告)号：US5825084A

公开(公告)日：1998-10-20

申请号：US795478

申请日：1997-02-11

申请人： John H. Lau ,  Yung Shih Chen ,  Tai-Yu Chou ,  Frank H. Wu ,  Kuan Luen Chen ,  Wei H. Koh

发明人： John H. Lau ,  Yung Shih Chen ,  Tai-Yu Chou ,  Frank H. Wu ,  Kuan Luen Chen ,  Wei H. Koh

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01L23/12 ,  H01L23/28

CPC分类号： H01L23/49805 ,  H01L23/4985 ,  H01L23/50 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15747

摘要： The present invention discloses a new substrate with two metal layer circuit structure and layout for semiconductor packaging. The speed and performance characteristics of the semiconductor device are optimized while the packaging structure is simplified by utilizing only one dielectric layer and conventional printed circuit board fabrication process. The difficulties encountered due to the complexities and higher cost of production required for the multiple layer and high density configuration are thus avoided. The improved circuit structure is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide inter-layer connections. In addition to the benefits of high performance, low cost, the improved circuit structure and package layout provide flexibility allowing higher degree of freedom for selecting the location and number of input and output signal lines and connections to the ground and power planes from the semiconductor device.

摘要翻译： 本发明公开了一种具有两个金属层电路结构和半导体封装布局的新基片。 通过仅使用一个电介质层和传统的印刷电路板制造工艺简化了封装结构，优化了半导体器件的速度和性能特性。 因此避免了由于多层和高密度构造所需的复杂性和更高的生产成本而遇到的困难。 改进的电路结构通过在衬底的一侧上实现分段环并在另一侧上实现分裂平面来实现，从而形成单层衬底结构。 衬底的边缘涂有金属层以提供层间连接。 除了高性能，低成本的优点之外，改进的电路结构和封装布局提供了灵活性，允许更高的自由度来选择输入和输出信号线的位置和数量以及从半导体器件到地面和电源平面的连接 。

公开(公告)号：US5717247A

公开(公告)日：1998-02-10

申请号：US751930

申请日：1996-11-05

申请人： Wei H. Koh ,  Connie S. McCausland

发明人： Wei H. Koh ,  Connie S. McCausland

IPC分类号： H05K1/11 ,  H01L21/48 ,  H01L23/538 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H01L23/48

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H05K3/4061 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/035 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09981 ,  H05K2203/1476 ,  H05K3/0094

摘要： A method for forming a conductive vias in a non-conductive substrate having a through-hole formed therein intermediate two side thereof. The method utilizes the steps of: applying gold paste to the through-hole so as to provide electrical conduction therethrough; and under firing the gold paste when a thin conductive film is present upon the substrate and fully firing the gold paste when no thin conductive film is present on the substrate. Under firing the gold paste when a thin-film is present upon the substrate prevents degradation of the thin conductive film. Subsequent processing of the gold paste assures the integrity and reliability thereof. Thus, the gold paste provides enhanced conductivity and improved reliability, as compared to contemporary thin-film vias.

摘要翻译： 一种用于在非导电衬底中形成导电通孔的方法，其中具有形成在其中间两侧的通孔。 该方法采用以下步骤：将金膏施加到通孔，以提供通过其的导电性; 并且当在基板上存在薄导电膜并且在基板上不存在薄导电膜时完全烧制金膏时，在烧结金膏时。 当在基板上存在薄膜时，在烧制金膏时，可以防止薄导电膜的劣化。 金膏的后续处理确保了其完整性和可靠性。 因此，与当代薄膜通孔相比，金膏提供增强的导电性和改进的可靠性。

公开(公告)号：US5075201A

公开(公告)日：1991-12-24

申请号：US607154

申请日：1990-10-31

申请人： Wei H. Koh

发明人： Wei H. Koh

IPC分类号： H01L21/60 ,  H01L23/544 ,  H01L27/146

CPC分类号： H01L24/81 ,  H01L23/544 ,  H01L27/1465 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10S430/145

摘要： A method for aligning infrared detector arrays having a high density of pixel elements to the surface of a signal processing module or the like is disclosed. The process comprises the steps of forming a plurality of indicia upon the second side of the infrared detector array, forming a corresponding plurality of reference indices upon the support surface, the indices being disposed in a predetermined position relative to the electrical connectors, attaching the second side of the infrared detector array to a transparent substrate and positioning the detector array adjacent the support surface and aligning the indicia to the reference indices by observing the indicia formed upon the second side of the array by looking through the transparent substrate. Three embodiments of indicia are disclosed. A through hole indicia passes from the first surface of the infrared detector array to the second surface thereof, a plurality of fiducial indicia can be formed upon the second surface of the infrared detector array, or notches can be formed in the edges of the infrared detector array and/or substrate.

摘要翻译： 公开了一种用于将具有高密度像素元件的红外探测器阵列与信号处理模块等的表面对准的方法。 该方法包括以下步骤：在红外检测器阵列的第二侧上形成多个标记，在支撑表面上形成对应的多个参考标记，指数相对于电连接器设置在预定位置， 将红外检测器阵列的一侧连接到透明基板，并将检测器阵列邻近支撑表面定位，并通过观察通过透明基底观察在阵列的第二侧上形成的标记来将标记对准参考索引。 公开了三个标记实施例。 通孔标记从红外检测器阵列的第一表面通过其第二表面，可以在红外检测器阵列的第二表面上形成多个基准标记，或者可以在红外检测器的边缘形成凹口 阵列和/或衬底。

公开(公告)号：US07781873B2

公开(公告)日：2010-08-24

申请号：US10424096

申请日：2003-04-28

申请人： Wei H. Koh ,  Fred Kong ,  David Chen

发明人： Wei H. Koh ,  Fred Kong ,  David Chen

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49524 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A thin, small outline IC leadframe plastic package to be used to assemble high performance, high speed semiconductor memory IC devices such as dynamic random access memories (DRAM) having a high data transfer rate in the range of 1 GigaHertz. The package leadframe is electrically interconnected to the IC device input-output pads by either electrically conductive (e.g. solder) bumps that are flip-chip bonded to the IC device or by of an interposer. The interposer contains integral curled micro-spring contacts at opposite ends of conductive fan out traces. The interposer is attached to the leadframe bonding pads by way of tape automated bonding, soldering, or adhesive bonding. The leadframe that is interconnected to the IC device by the aforementioned flip-chip bumps or the interposer is encapsulated and trimmed to form either gull-wing style perimeter leads as a standard thin small outline package (TSOP) or wrap around leads as a micro-leadframe (MLF) package.

摘要翻译： 用于组装高性能，高速半导体存储器IC器件的薄型小外形IC引线框塑料封装，例如具有在1千兆赫兹范围内的高数据传输速率的动态随机存取存储器（DRAM）。 封装引线框架通过倒装芯片接合到IC器件或通过插入器的导电（例如焊料）凸块与IC器件输入 - 输出焊盘电互连。 内插器在导电扇出的轨迹的相对端包含整体卷曲的微弹簧触点。 插入器通过带自动接合，焊接或粘合粘合附接到引线框接合焊盘。 通过上述倒装芯片凸块或插入器与IC器件互连的引线框架被封装和修整，以形成作为标准薄小外形封装（TSOP）的鸥翼型周边引线，或作为微型封装引线， 引线框（MLF）封装。

公开(公告)号：US5464979A

公开(公告)日：1995-11-07

申请号：US254134

申请日：1994-06-06

申请人： Wei H. Koh

发明人： Wei H. Koh

IPC分类号： G01S3/784 ,  G01S7/02 ,  G01S7/495 ,  H04N5/33 ,  G01S5/16

CPC分类号： G01S3/784 ,  G01S7/021 ,  G01S7/495 ,  H04N5/33

摘要： A multi-directional infrared detector system provides multi-view or surround-view imaging which is particularly suited for use in tactical battlefield situations. The system utilizes a plurality of infrared detector arrays disposed in a generally circular configuration, each of the infrared detector arrays having a plurality of infrared detector elements formed thereon; a corresponding plurality of dedicated optics assemblies for forming images upon the infrared detector arrays; and at least one conductive conduit supporting layer having conductive conduits formed thereon. The conductive conduit support layer extends inwardly from each of the infrared detector arrays to a core defined by the infrared detector arrays. Signal conditioning circuitry is disposed generally at the core of the infrared detector arrays such that signals representative of the outputs of the infrared detector elements are communicated from the detector elements to the signal processing circuitry via the conductive conduits.

摘要翻译： 多方向红外探测器系统提供了特别适用于战术战场情况的多视角或环绕立体成像。 该系统利用以大致圆形配置设置的多个红外检测器阵列，每个红外检测器阵列具有形成在其上的多个红外检测器元件; 用于在红外检测器阵列上形成图像的相应的多个专用光学组件; 以及在其上形成有导电导管的至少一个导电导管支撑层。 导电导管支撑层从每个红外探测器阵列向内延伸到由红外探测器阵列限定的核心。 信号调理电路通常设置在红外检测器阵列的核心处，使得表示红外检测器元件的输出的信号经由导电导管从检测器元件传送到信号处理电路。

公开(公告)号：US07317250B2

公开(公告)日：2008-01-08

申请号：US10952891

申请日：2004-09-30

申请人： Wei H. Koh ,  David Chen

发明人： Wei H. Koh ,  David Chen

IPC分类号： H01L23/34

CPC分类号： H05K1/182 ,  G11C5/02 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10689 ,  H01L2924/00

摘要： A high density memory card assembly having application for USB drive storage, flash and ROM memory cards, and similar memory card formats. A cavity is formed through a rigid laminate substrate. First and second digital memory devices (e.g., TSOP packages or bare semiconductor dies) are located within the cavity so as to be recessed relative to the top and bottom of the substrate. The recessed first and second memory devices are arranged in spaced, face-to-face alignment with one another within the cavity. The first and second memory devices are covered and protected by respective first and second memory packages that are located on the top and bottom of the substrate. By virtue of the foregoing, the memory package density of the assembly can be increased without increasing the height or area consumed by the assembly for receipt within an existing external housing.

摘要翻译： 适用于USB驱动器存储，闪存和ROM存储卡以及类似存储卡格式的高密度存储卡组件。 通过刚性层压基板形成空腔。 第一和第二数字存储器件（例如，TSOP封装或裸半导体管芯）位于空腔内，以便相对于衬底的顶部和底部凹陷。 凹陷的第一和第二存储器件在空腔内彼此间隔开地面对面地排列。 第一和第二存储器件被位于衬底顶部和底部的相应的第一和第二存储器封装覆盖和保护。 由于上述原因，可以增加组件的存储器封装密度，而不会增加组件消耗的高度或面积，以便在现有的外部外壳内接收。

公开(公告)号：US06737738B2

公开(公告)日：2004-05-18

申请号：US10195995

申请日：2002-07-16

申请人： Wei H. Koh ,  David H. Chen

发明人： Wei H. Koh ,  David H. Chen

IPC分类号： H01L2302

CPC分类号： G11C5/04 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/00014 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

摘要： A high density, low profile, three dimensional memory module having multi-level semiconductor packages mounted on one or opposite sides of a printed wiring board. Each multi-level package of the memory module contains an upper level DRAM integrated circuit package that is surface mounted on the printed wiring board and at least one lower level DRAM integrated circuit package that is surface mounted on the printed wiring board below the upper level package, such that the upper and lower level packages are stacked one above the other. The upper level package is preferably a thin small outline package, and the lower level package is preferably a leadless chip scale package. The leads of the upper level package are of sufficient length so that the standoff height of the upper level package establishes a clearance thereunder in which to receive the lower level package. The lower level package is characterized by a smaller footprint and profile than the corresponding footprint and profile of the upper level package.

摘要翻译： 具有安装在印刷电路板的一侧或相对侧上的多层半导体封装的高密度，低剖面的三维存储器模块。 存储器模块的每个多级封装包含表面安装在印刷电路板上的上层DRAM集成电路封装以及表面安装在上层封装之下的印刷电路板上的至少一个下层DRAM集成电路封装 ，使得上层和下层包装层叠在另一层之上。 上层包装优选为薄的小外形封装，较低级封装优选为无引线芯片级封装。 上层包装的引线具有足够的长度，使得上层包装的间隔高度在其下方形成了用于接收较低级包装的间隙。 较低级别的封装的特征在于比上层封装的相应占位面积和外形更小的占地面积和外形。

公开(公告)号：US5138164A

公开(公告)日：1992-08-11

申请号：US729572

申请日：1991-07-15

申请人： Wei H. Koh

发明人： Wei H. Koh

IPC分类号： G02B5/20 ,  H01L31/0232

CPC分类号： G02B5/201 ,  H01L31/0232

摘要： An infrared detector subarray having an integral filter assembly is comprised of a plurality of stacked modules defining an infrared detector focal plane subarray; a filter plate sized and configured to correspond to the infrared detector subarray; and a plurality of supports disposed intermediate the filter plate and the detector subarray for attaching the filter plate to the subarray such that the filter plate is in close proximity to the detector subarray. Scattering and crossstalk are minimized by positioning the filter plate in close proximity to the detector subarray. The supports may comprise planar members having a thickness of less than approximately 0.003 inch such that they may be disposed intermediate adjacent modules. The filter plate may further comprise a plurality of parallel stripes, each parallel stripe transmitting infrared radiation of a different frequency than that transmitted by adjacent stripes such that a focal plane array comprised thereof may be sensitive to infrared radiation at a plurality of frequencies. Forming the filter as an integral part of the subarrays eliminates the need to fabricate a single filter having a diameter of two feet or more. The infrared detector subarray and integral filter assembly of the present invention provide for the fabrication of a filter which is easier to fabricate, has a higher fabrication yield, is lighter in weight, has improved mechanical stability, and facilitates more reliable testing.

摘要翻译： 具有整体滤光器组件的红外探测器子阵列由限定红外检测器焦平面子阵列的多个堆叠模块组成; 尺寸和构造为对应于红外检测器子阵列的滤板; 以及设置在过滤板和检测器子阵列之间的多个支撑件，用于将过滤板附接到子阵列，使得过滤板紧邻检测器子阵列。 通过将滤板放置在检测器子阵列附近，使散射和串扰最小化。 支撑件可以包括具有小于约0.003英寸的厚度的平面构件，使得它们可以设置在相邻模块之间。 过滤板还可以包括多个平行条纹，每个平行的条纹发射的频率与由相邻条带传播的频率不同的红外辐射，使得由其组成的焦平面阵列可能对多个频率的红外辐射敏感。 将过滤器形成为子阵列的组成部分消除了制造直径为2英尺或更大的单个过滤器的需要。 本发明的红外检测器子阵列和一体式过滤器组件提供了制造更容易制造的过滤器，制造成本更高，重量更轻，机械稳定性提高，便于更可靠的测试。

公开(公告)号：US5135556A

公开(公告)日：1992-08-04

申请号：US767614

申请日：1991-09-30

申请人： William B. Hornback ,  Wei H. Koh

发明人： William B. Hornback ,  Wei H. Koh

IPC分类号： H01L25/16 ,  H05K1/03 ,  H05K3/46

CPC分类号： H05K3/4629 ,  H01L25/167 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/068

摘要： A fused high density multi-layered integrated circuit module for integrating infrared detector arrays to signal conditioning circuits is disclosed. The module comprises a plurality of thin film substrate layers disposed in substantially overlapping registry to form a non-conductive supporting body, a plurality of the layers have electronic devices mounted thereon. A plurality of detector element connectors are formed along a first edge portion of the body. Conductive conduits are formed upon a plurality of the layers. The conductive conduits have first portions which interconnect the detector element connectors to the electronic devices disposed upon the layers of the body. The conductive conduits also have second portions formed upon the surface of said layers and extending to the second edge portion thereof for communicating signals between the electronic devices and external electronics. A glass binding material adhesively attaches adjacent substrate layers together. The glass binding material has a coefficient of expansion of the substrate layers such that thermal stress is reduced and the need for a buffer board is consequently eliminated.

摘要翻译： 公开了一种用于将红外探测器阵列集成到信号调理电路的融合的高密度多层集成电路模块。 该模块包括设置在基本上重叠的配准器中的多个薄膜基底层，以形成非导电支撑体，多个层具有安装在其上的电子器件。 沿着身体的第一边缘部分形成多个检测器元件连接器。 导电导管形成在多个层上。 导电管道具有将检测器元件连接器与设置在主体层上的电子设备互连的第一部分。 导电导管还具有形成在所述层的表面上并延伸到其第二边缘部分的第二部分，用于在电子设备和外部电子器件之间传递信号。 玻璃粘合材料将相邻的基底层粘附在一起。 玻璃粘合材料具有基底层的膨胀系数，使得热应力降低，从而消除对缓冲板的需要。

公开(公告)号：US08071895B2

公开(公告)日：2011-12-06

申请号：US12691683

申请日：2010-01-21

申请人： George Shiu ,  Wei H. Koh

发明人： George Shiu ,  Wei H. Koh

IPC分类号： H05K5/06

CPC分类号： H05K5/064 ,  H01R13/5216 ,  H05K3/284 ,  H05K5/0278 ,  H05K2203/1322 ,  Y10T29/49117

摘要： A data storage device and methods of manufacture are provided which tend to protect the device against moisture and shock. The device includes a circuit board, a coating, a housing, and preferably a sealant. The circuit board is in electrical communication with an electrical interface. The coating is disposed at least on the circuit board to generally encapsulate the circuit board. The housing is sized and configured to generally encompass the circuit board and the coating. The housing includes a housing opening being sized and configured with the electrical interface being at least partially exposed therethrough. The sealant is preferably disposed within the housing substantially intermediate the interior surface of the housing and the coating on the circuit board. Further, at least one of the coating and the sealant may be disposed substantially intermediate the electrical interface and the housing opening.

摘要翻译： 提供了一种数据存储装置和制造方法，其倾向于保护装置免受潮湿和冲击。 该装置包括电路板，涂层，壳体，优选密封剂。 电路板与电气接口电气通信。 涂层至少设置在电路板上以通常封装电路板。 外壳的尺寸和构造大致包含电路板和涂层。 壳体包括壳体开口，其尺寸和构造具有至少部分地暴露在其中的电接口。 密封剂优选地设置在壳体内，基本上位于壳体的内表面和电路板上的涂层之间。 此外，涂层和密封剂中的至少一个可以基本上设置在电接口和壳体开口的中间。