公开(公告)号：US20250167187A1

公开(公告)日：2025-05-22

申请号：US18628173

申请日：2024-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

公开(公告)号：US20250167129A1

公开(公告)日：2025-05-22

申请号：US19028395

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

公开(公告)号：US20250167047A1

公开(公告)日：2025-05-22

申请号：US19027412

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  Wei-Jung Lin ,  Hsien-Lung Yang ,  Yu-Kai Chen ,  Hong-Mao Lee

IPC: H01L21/768 ,  H10D30/01 ,  H10D30/62 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

公开(公告)号：US20250159998A1

公开(公告)日：2025-05-15

申请号：US19020097

申请日：2025-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Chung-Hsing WANG ,  Yi-Kan CHENG

IPC: H10D89/10 ,  G06F111/20 ,  H10D84/85

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

公开(公告)号：US20250159904A1

公开(公告)日：2025-05-15

申请号：US19021415

申请日：2025-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Wen-Ting CHU ,  Yong-Shiuan TSAIR ,  Yu-Wen LIAO ,  Chih-Yang CHANG ,  Chin-Chieh YANG

IPC: H10B63/00 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a metal/dielectric layer, a second dielectric layer, a bottom electrode, a resistance switch element, and a top electrode. The metal/dielectric layer has a first dielectric layer and a conductive feature in the first dielectric layer. The second dielectric layer is over the metal/dielectric layer. The bottom electrode is over and in contact with the conductive feature and surrounded by the second dielectric layer. The second dielectric layer has a tapered sidewall, a lower portion of the tapered sidewall of the second dielectric layer is covered by the bottom electrode, and an upper portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode. The resistance switch element is over the bottom electrode. The top electrode is over the resistance switch element.

公开(公告)号：US20250157919A1

公开(公告)日：2025-05-15

申请号：US19024920

申请日：2025-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu CHEN ,  Chung-Liang CHENG

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

公开(公告)号：US20250157876A1

公开(公告)日：2025-05-15

申请号：US19021576

申请日：2025-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L23/367 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

公开(公告)号：US20250157818A1

公开(公告)日：2025-05-15

申请号：US18506864

申请日：2023-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Lin WEI ,  Ching-Yu CHANG

IPC: H01L21/027 ,  G03F7/038 ,  G03F7/32 ,  G03F7/38 ,  H01L21/311

Abstract: A method for forming a semiconductor device is provided. The methods includes forming a photoresist layer over a substrate. The photoresist layer includes a polymer and an photoacid generator (PAG). The polymer includes a polymer backbone, an etch resistance promoting group chemically bonded to the polymer backbone, and an acid labile group (ALG) chemically bonded to the etch resistance promoting group. The method further includes exposing a portion of the photoresist layer to a radiation to produce acid in exposed portion, baking the photoresist layer, resulting in cleavage of the ALG, and removing an portion of the photoresist layer to form a patterned photoresist layer.

公开(公告)号：US12302640B2

公开(公告)日：2025-05-13

申请号：US18355895

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H10D87/00 ,  H01L21/762 ,  H10D30/62 ,  H10D30/67 ,  H10D62/10 ,  H10D62/17 ,  H10D62/40 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D86/00 ,  H10D86/01

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US12302609B2

公开(公告)日：2025-05-13

申请号：US18596115

申请日：2024-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L21/02 ,  H01L21/306 ,  H10B20/00 ,  H10B20/25 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.