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    Semiconductor memory, memory device, and memory card
    5.
    发明授权
    Semiconductor memory, memory device, and memory card 有权
    半导体存储器，存储器件和存储卡

    公开(公告)号：US06757853B2

    公开(公告)日：2004-06-29

    申请号：US10244539

    申请日：2002-09-17

    申请人： Masashi Wada ,  Takao Okubo ,  Takeshi Furuno

    发明人： Masashi Wada ,  Takao Okubo ,  Takeshi Furuno

    IPC分类号： G11C2900

    CPC分类号： G11C29/70 ,  G11C29/88

    摘要： A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.

    摘要翻译： 提供封装在一个封装中的存储器件，其包括集成在一个半导体衬底中的第一数据端子，第一地址端子，状态端子和存储器芯片，存储器芯片之一是非易失性存储器。 每个存储芯片包括数据终端和地址终端。 每个存储器芯片的数据端子连接到第一数据端子，并且每个存储器芯片的地址端子连接到第一地址端子。 状态终端被配置为输出指示何时非易失性存储器处于就绪状态或处于忙状态的状态信号。

    Batch erasable nonvolatile memory device and erasing method
    8.
    发明授权
    Batch erasable nonvolatile memory device and erasing method 失效
    批量可擦除非易失性存储器件和擦除方法

    公开(公告)号：US5598368A

    公开(公告)日：1997-01-28

    申请号：US445105

    申请日：1995-05-19

    申请人： Masahito Takahashi ,  Michiko Odagiri ,  Takeshi Furuno ,  Kazunori Furusawa ,  Masashi Wada

    发明人： Masahito Takahashi ,  Michiko Odagiri ,  Takeshi Furuno ,  Kazunori Furusawa ,  Masashi Wada

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C13/00

    CPC分类号： G11C16/3477 ,  G11C16/16 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3468

    摘要： A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.

    摘要翻译： 批量可擦除非易失性存储装置和使用该存储器单元的装置，该存储单元适于通过通过编程操作（包括预写操作）弹出在浮动栅极上累积的电荷来执行擦除操作， 序列，用于读取擦除单元的存储单元并且在不存储电荷的浮动栅极上对那些非易失性存储单元执行预写操作的第一操作，用于在存储单元中执行批量擦除操作的第二操作 在相对较大的擦除参考电压下具有相对大的能量的所述擦除单元的非易失性存储单元的高速度，用于执行所有擦除的非易失性存储单元的读操作的第三操作和对那些非易失性存储单元的写操作 适于具有相对低的阈值电压，以及第四操作，用于以低速执行批量擦除操作 所述擦除单元的非易失性存储单元在相对小的擦除参考电压下具有相对小的能量，或者设置有用于执行这些操作的自动擦除电路。

    Semiconductor integrated circuit operable and programmable at multiple voltage levels
    9.
    发明授权
    Semiconductor integrated circuit operable and programmable at multiple voltage levels 失效
    半导体集成电路在多个电压电平下可操作和可编程

    公开(公告)号：US5444663A

    公开(公告)日：1995-08-22

    申请号：US893802

    申请日：1992-06-04

    申请人： Takeshi Furuno ,  Yasuhiro Nakamura ,  Akinori Matsuo

    发明人： Takeshi Furuno ,  Yasuhiro Nakamura ,  Akinori Matsuo

    IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C8/00

    CPC分类号： G11C5/143

    摘要： Each internal circuit of a semiconductor integrated circuit operates at both a relatively high operating voltage having a predetermined allowable range and a relatively low operating voltage also having a predetermined allowable range. The operating voltage is externally supplied. Operating conditions of the semiconductor integrated circuit are individually set restrictive to the relatively high operating voltage having a predetermined allowable range and to the relatively low operating voltage having a predetermined allowable range. The semiconductor integrated circuit is operable selectively at these operating voltages. Since the internal circuits are operated at two operating voltages, an arrangement of internal circuits can be simplified while the semiconductor integrated circuit is concurrently usable in not only the conventional system but also a low-voltage one. Moreover, an operating method of the sort that conforms to specifications restrictive of both the relatively high operating voltage as used in the conventional system and the low-voltage system renders a simply constructed integrated circuit with an extendable a range of uses.

    摘要翻译： 半导体集成电路的每个内部电路在具有预定容许范围的相对较高的工作电压和也具有预定容许范围的较低工作电压的情况下工作。 外部提供工作电压。 半导体集成电路的工作条件被分别设定为具有预定容许范围的较高工作电压和具有预定容许范围的较低工作电压。 半导体集成电路可在这些工作电压下选择性地工作。 由于内部电路在两个工作电压下操作，所以可以简化内部电路的布置，而半导体集成电路不仅可以在常规系统中使用，而且可以用于低电压。 此外，符合限制常规系统中使用的相对高的工作电压的规格的操作方法和低电压系统使得简单构造的集成电路具有可扩展的使用范围。