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公开(公告)号：US5598368A
公开(公告)日：1997-01-28
申请号：US445105
申请日：1995-05-19
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3409 , G11C16/3445 , G11C16/3468
摘要： A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.
摘要翻译： 批量可擦除非易失性存储装置和使用该存储器单元的装置，该存储单元适于通过通过编程操作（包括预写操作）弹出在浮动栅极上累积的电荷来执行擦除操作， 序列，用于读取擦除单元的存储单元并且在不存储电荷的浮动栅极上对那些非易失性存储单元执行预写操作的第一操作，用于在存储单元中执行批量擦除操作的第二操作 在相对较大的擦除参考电压下具有相对大的能量的所述擦除单元的非易失性存储单元的高速度，用于执行所有擦除的非易失性存储单元的读操作的第三操作和对那些非易失性存储单元的写操作 适于具有相对低的阈值电压，以及第四操作，用于以低速执行批量擦除操作 所述擦除单元的非易失性存储单元在相对小的擦除参考电压下具有相对小的能量，或者设置有用于执行这些操作的自动擦除电路。
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2.发明授权Batch erasable single chip nonvolatile memory device and erasing method therefor 失效批量可擦式单片非易失性存储器件及其擦除方法
公开(公告)号：US5898621A
公开(公告)日：1999-04-27
申请号：US904276
申请日：1997-07-31
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3409 , G11C16/3445 , G11C16/3468
摘要： A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltages, or is provided with an automatic erasing circuit for executing these operations.
摘要翻译： 批量可擦除单芯片非易失性存储器件及其使用方法，其具有存储单元，该存储单元适于通过通过编程操作（包括预写操作）在浮动栅极上累积的电荷来执行擦除操作， 依次执行用于读取擦除单元的存储单元的第一操作，并对不存储电荷的浮动栅极上的那些非易失性存储单元执行预写操作，执行批次擦除的第二操作 在相对大的擦除参考电压下，具有相对大的能量的所述擦除单元的非易失性存储单元的高速操作，用于执行所有擦除的非易失性存储单元的读操作的第三操作和对那些非易失性存储单元的写操作 适于具有相对低的阈值电压的存储单元，以及用于在a处执行批量擦除操作的第四操作 或者具有用于执行这些操作的自动擦除电路，所述擦除单元的非易失性存储单元的低速度具有相对小的能量。
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公开(公告)号：US5677868A
公开(公告)日：1997-10-14
申请号：US741938
申请日：1996-10-31
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3409 , G11C16/3445 , G11C16/3468
摘要： A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.
摘要翻译： 批量可擦除非易失性存储器件和使用该存储单元的设备具有存储单元的装置，该存储单元适于通过通过编程操作（包括预写操作）在浮动栅极处累积的电荷来执行擦除操作， 依次进行第一操作，用于读取擦除单元的存储单元并对不存储电荷的浮动栅极上的那些非易失性存储单元执行预写操作，第二操作用于执行批量擦除操作 在相对大的擦除参考电压下具有相对较大能量的所述擦除单元的非易失性存储单元的高速，用于执行所有擦除的非易失性存储单元的读取操作的第三操作和对这些非易失性存储单元的写入操作 其适于具有相对低的阈值电压，以及用于以低速执行批量擦除操作的第四操作 所述擦除单元的非易失性存储单元在相对小的擦除参考电压下具有相对小的能量，或者设置有用于执行这些操作的自动擦除电路。
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公开(公告)号：US5455789A
公开(公告)日：1995-10-03
申请号：US241274
申请日：1994-05-10
摘要： Two paths for receiving the outputs of a logic select circuit LOGS are individually equipped in a symmetric manner with output MOSFETs Q52 and Q53, feedback MOSFETs Q54 and Q55 and isolating MOSFETs Q56 and Q57, the paired of which have conduction types different from each other. Negative erasing Vee voltage and programming Vpp voltage to be fed to the paths through the feedback MOSFETs are prevented without fail from being transmitted to a logic select circuit by the paired isolating MOSFETs of the different conduction types. As the elements for selecting the positive or negative logic output of the logic select circuit, CMOS transfer gates TG1 and TG2 can be adopted to maximize the amplitude of the output logic signal of the logic select circuit with respect to an operating power.
摘要翻译： 用于接收逻辑选择电路LOGS的输出的两个路径以对称的方式与输出MOSFET Q52和Q53，反馈MOSFET Q54和Q55以及隔离MOSFET Q56和Q57（其一对具有彼此不同的导电类型）分别装备。 负消除通过反馈MOSFET馈入到路径的Vee电压和编程Vpp电压被防止，而不会被不同导通类型的成对隔离MOSFET传输到逻辑选择电路。 作为用于选择逻辑选择电路的正或负逻辑输出的元件，可以采用CMOS传输门TG1和TG2来使逻辑选择电路的输出逻辑信号的幅度相对于工作功率最大化。
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公开(公告)号：US06266792B1
公开(公告)日：2001-07-24
申请号：US09427068
申请日：1999-10-26
申请人： Masashi Wada , Takao Okubo , Takeshi Furuno
发明人： Masashi Wada , Takao Okubo , Takeshi Furuno
IPC分类号： G11C2900
摘要： A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data-input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.
摘要翻译： 一种半导体存储器（1），包括设置有大量存储单元的多个存储块（2和3），数据输入/输出缓冲器（7）和用于控制重写和读取的第一控制装置 存储单元的数据设置有用于指定部分缺陷存储块的第一存储装置（30）和用于根据地址信号检测由第一存储装置指定的缺陷存储块的访问的检测装置（32）。 在这种情况下，当检测装置检测到对缺陷存储器的访问时，第一控制装置禁止用于数据重写操作的指令的数据重写操作，并且禁止数据输入/输出缓冲器的数据输出操作用于指令 数据读取操作。 禁止功能使得可以仅通过组合具有不可弥补缺陷的半导体存储器来提供具有与无缺陷半导体存储器的兼容性的存储器件，而不固定特定地址输入端子的电平，以便保持有缺陷的存储块非选择性。
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公开(公告)号：US06016560A
公开(公告)日：2000-01-18
申请号：US981094
申请日：1998-03-17
申请人： Masashi Wada , Takao Okuba , Takeshi Furuno
发明人： Masashi Wada , Takao Okuba , Takeshi Furuno
摘要： A semiconductor memory (1), having a plurality of memory blocks (2 and 3) provided with a plurality of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating defective memory blocks and detection means (32) for detecting an access to a defective memory block designated by the first storage means in accordance with an address signal. When the detection means detects an access to a defective memory, the first control means inhibits the data rewrite operation for an instruction for a data rewrite operation and inhibits the output of data from the input/output buffer for the data read operation. The inhibiting function makes it possible to provide a memory device having compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.
摘要翻译： PCT No.PCT / JP96 / 01447 Sec。 371日期：1998年3月17日 102（e）1998年3月17日PCT PCT 1996年5月29日PCT公布。 出版物WO97 / 00518 日期1997年1月3日具有设置有多个存储单元的多个存储块（2和3），数据输入/输出缓冲器（7）和控制装置（11）的半导体存储器（1） 提供存储单元的数据的重写和读取用于指定缺陷存储块的第一存储装置（30）和用于根据地址检测对由第一存储装置指定的缺陷存储块的访问的检测装置（32） 信号。 当检测装置检测到对缺陷存储器的访问时，第一控制装置禁止用于数据重写操作的指令的数据重写操作，并且禁止用于数据读取操作的来自输入/输出缓冲器的数据的输出。 抑制功能使得可以仅通过组合具有不可弥补缺陷的半导体存储器来提供具有与无缺陷半导体存储器的兼容性的存储器件，而不固定特定地址输入端子的电平，以便保持有缺陷的存储块非选择性。
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公开(公告)号：US06757853B2
公开(公告)日：2004-06-29
申请号：US10244539
申请日：2002-09-17
申请人： Masashi Wada , Takao Okubo , Takeshi Furuno
发明人： Masashi Wada , Takao Okubo , Takeshi Furuno
IPC分类号： G11C2900
摘要： A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.
摘要翻译： 提供封装在一个封装中的存储器件，其包括集成在一个半导体衬底中的第一数据端子，第一地址端子，状态端子和存储器芯片，存储器芯片之一是非易失性存储器。 每个存储芯片包括数据终端和地址终端。 每个存储器芯片的数据端子连接到第一数据端子，并且每个存储器芯片的地址端子连接到第一地址端子。 状态终端被配置为输出指示何时非易失性存储器处于就绪状态或处于忙状态的状态信号。
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公开(公告)号：US06477671B2
公开(公告)日：2002-11-05
申请号：US09845350
申请日：2001-05-01
申请人： Masashi Wada , Takao Okubo , Takeshi Furuno
发明人： Masashi Wada , Takao Okubo , Takeshi Furuno
IPC分类号： G11C2900
摘要： A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.
摘要翻译： 一种半导体存储器（1），包括设置有大量存储单元的多个存储块（2和3），数据输入/输出缓冲器（7）和用于控制数据的重写和读取的第一控制装置（11） 为存储单元设置有用于指定部分缺陷存储块的第一存储装置（30）和用于根据地址信号检测由第一存储装置指定的缺陷存储块的存取的检测装置（32）。 在这种情况下，当检测装置检测到对缺陷存储器的访问时，第一控制装置禁止用于数据重写操作的指令的数据重写操作，并且禁止数据输入/输出缓冲器的数据输出操作用于指令 数据读取操作。 禁止功能使得可以仅通过组合具有不可弥补缺陷的半导体存储器来提供具有与无缺陷半导体存储器的兼容性的存储器件，而不固定特定地址输入端子的电平，以便保持有缺陷的存储块非选择性。
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公开(公告)号：US07704465B2
公开(公告)日：2010-04-27
申请号：US10289429
申请日：2002-11-07
申请人： Hisakatsu Kato , Masashi Wada , Naoyuki Eguchi , Hirofumi Sasaki
发明人： Hisakatsu Kato , Masashi Wada , Naoyuki Eguchi , Hirofumi Sasaki
IPC分类号： B01J19/18
CPC分类号： B01F7/00208 , B01F7/00641 , B01F7/1675 , B01F7/22 , B01F15/00837 , B01F2215/0431 , B01F2215/044 , B01F2215/0472 , B01F2215/0477 , B01J19/006 , B01J19/0066 , B01J19/1812 , B01J2219/00768 , C01F7/02 , C01F7/14 , C01F7/144 , C01F7/147 , C01P2004/50 , C01P2004/61 , C01P2006/60 , C09C1/407 , Y10T428/2982
摘要： Aluminum hydroxide aggregated particles which have an average particle diameter of not less than 40 μm, an average particle diameter as determined after pressing at 1,000 kg/cm2 of not more than 35 μm, and an L value of slurry obtained by mixing 20 ml of glycerol and 10 g of the aluminum hydroxide aggregated particles of not more than 69, are obtained by a process comprising the steps of: (a) feeding a supersaturated aqueous sodium aluminate solution to a vessel, (b) adding aluminum hydroxide seeds to the supersaturated aqueous sodium aluminate solution, (c) stirring the seed-added solution in the vessel while continuously feeding an additional supersaturated aqueous sodium aluminate solution into the vessel to hydrolyze the supersaturated aqueous sodium aluminate solution, (d) separating the aluminum hydroxide aggregated particles from the aqueous sodium aluminate solution, and (e) continuously discharging the aqueous sodium aluminate solution out of the vessel.
摘要翻译： 平均粒径为40μm以上的氢氧化铝凝集粒子，1000kg / cm 2以上压制后测定的平均粒径为35μm以下，通过将20ml甘油 和10g不超过69的氢氧化铝凝集颗粒，通过包括以下步骤的方法获得：（a）将过饱和的铝酸钠水溶液进料到容器中，（b）将氢氧化铝种子加入到过饱和水溶液 铝酸钠溶液，（c）在容器中搅拌添加种子的溶液，同时连续向容器中加入过饱和的铝酸钠水溶液以水解过饱和的铝酸钠水溶液，（d）将氢氧化铝凝集颗粒与水溶液 铝酸钠溶液，和（e）将铝酸钠水溶液连续排出容器。
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公开(公告)号：US07661744B2
公开(公告)日：2010-02-16
申请号：US12105675
申请日：2008-04-18
申请人： Yuuki Maruno , Masashi Wada
发明人： Yuuki Maruno , Masashi Wada
IPC分类号： B60N2/20
CPC分类号： B60N2/015 , B60N2/22 , B60N2205/30
摘要： A pair of seat backs are arranged in a vehicle width direction. A pair of floor brackets attach outer end portions of the seat backs in the vehicle width direction to a floor of the vehicle. A pair of center hinge brackets attach inner end portions of the seat backs in the vehicle width direction to the floor. A supporting bar is separated from the floor, is extended in the vehicle width direction and is disposed behind the seat backs. The seat backs are independently pivotably attached to the floor. Both end portions of the supporting bar in the vehicle width direction are attached to the floor brackets. A center portion of the supporting bar in the vehicle width direction is attached to the center hinge brackets.
摘要翻译： 一对座椅靠背沿车宽方向排列。 一对地板支架将车座宽度方向上的座椅靠背的外端部附接到车辆的地板。 一对中心铰链支架将座椅靠背的车身宽度方向的内端部与地板相连。 支撑杆与地板分离，沿车宽方向延伸并设置在座椅靠背后面。 座椅靠背独立地可枢转地连接到地板上。 支撑杆的车宽方向的两端部附接到地板支架。 支撑杆的车宽方向的中心部分附接到中心铰链支架。
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