公开(公告)号：US20120153355A1

公开(公告)日：2012-06-21

申请号：US13402631

申请日：2012-02-22

申请人： Hidekazu UMEDA ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hidekazu UMEDA ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/78

CPC分类号： H01L29/2003 ,  H01L29/1066 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

摘要： A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

摘要翻译： 氮化物半导体器件包括半导体衬底和形成在半导体衬底上的氮化物半导体层。 半导体衬底包括正常区域和围绕法线区域的界面电流阻挡区域。 氮化物半导体层包括元件区域和围绕元件区域的隔离区域。 元件区域形成在正常区域上。 界面电流阻挡区域含有杂质，并且在氮化物半导体层和半导体衬底之间的界面处产生的载流子形成势垒。

公开(公告)号：US20120126290A1

公开(公告)日：2012-05-24

申请号：US13360275

申请日：2012-01-27

申请人： Yasuhiro UEMOTO ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Yasuhiro UEMOTO ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7783

摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

摘要翻译： 氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。 位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域 形成有具有比控制区域更高的电阻的高电阻区域。

公开(公告)号：US20110297960A1

公开(公告)日：2011-12-08

申请号：US13213967

申请日：2011-08-19

申请人： Kenichiro Tanaka ,  Tetsuzo Ueda ,  Hisayoshi Matsuo ,  Masahiro Hikita

发明人： Kenichiro Tanaka ,  Tetsuzo Ueda ,  Hisayoshi Matsuo ,  Masahiro Hikita

IPC分类号： H01L21/60 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L23/053 ,  H01L23/562 ,  H01L29/2003 ,  H01L29/225 ,  H01L29/452 ,  H01L29/475 ,  H01L2224/72 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/00

摘要： A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer.

摘要翻译： 晶体管组件的制造方法包括以下步骤：（a）形成晶体管; （b）抛光基底; 和（c）将基底基板抛光的晶体管固定到支撑基板上。 步骤（a）是在基底基板的主表面上形成第一半导体层和第二半导体层的工序。 步骤（b）是对基材的与主面相反的表面进行研磨的工序。 步骤（c）是在施加到基底基板上的应力存在下，使晶体管固定在支撑基板上，使基板的翘曲减小的方向。 基底由不同于第一半导体层和第二半导体层的材料制成，并且在第二半导体层上施加拉伸应力。

公开(公告)号：US20110272740A1

公开(公告)日：2011-11-10

申请号：US13185818

申请日：2011-07-19

申请人： Hidekazu UMEDA ,  Masahiro HIKITA ,  Tetsuzo UEDA

发明人： Hidekazu UMEDA ,  Masahiro HIKITA ,  Tetsuzo UEDA

IPC分类号： H01L29/80 ,  H01L21/335

CPC分类号： H01L29/7783 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.

摘要翻译： 场效应晶体管包括形成在衬底上的第一半导体层和第二半导体层。 第一半导体层具有设置为包含非导电杂质的隔离区域的含有区域和不含非导电杂质的非含有区域。 第一区域由容纳区域和非含有区域之间的界面的一部分的附近限定，界面的部分在栅电极下方，包括界面部分的附近包含在包含 地区。 第二半导体层包括位于第一区域正上方的第二区域。 第二区域的非导电杂质的浓度低于第一区域的浓度。

公开(公告)号：US20110227093A1

公开(公告)日：2011-09-22

申请号：US13150574

申请日：2011-06-01

申请人： Masahiro HIKITA ,  Hidetoshi ISHIDA ,  Tetsuzo UEDA

发明人： Masahiro HIKITA ,  Hidetoshi ISHIDA ,  Tetsuzo UEDA

IPC分类号： H01L29/20 ,  H01L21/337 ,  H01L29/808

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/808

摘要： The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.

摘要翻译： 本发明的目的是提供一种能够增加阈值电压以及降低导通电阻的FET和FET的制造方法。 本发明的FET包括第一未掺杂的GaN层; 形成在第一未掺杂的GaN层上的第一未掺杂的AlGaN层，其带隙能量大于第一未掺杂的GaN层的带隙能量; 形成在第一未掺杂的AlGaN层上的第二未掺杂的GaN层; 形成在所述第二未掺杂GaN层上的第二未掺杂AlGaN层，具有大于所述第二未掺杂GaN层的带隙能量的带隙能量; 形成在第二未掺杂AlGaN层的凹部中的p型GaN层; 形成在p型GaN层上的栅电极; 以及形成在所述栅电极的两个横向区域中的源电极和漏电极，其中在所述第一未掺杂的GaN层和所述第一未掺杂的AlGaN层之间的异质结界面处形成沟道。

公开(公告)号：US08003975B2

公开(公告)日：2011-08-23

申请号：US11600101

申请日：2006-11-16

申请人： Tetsuzo Ueda ,  Tsuyoshi Tanaka

发明人： Tetsuzo Ueda ,  Tsuyoshi Tanaka

IPC分类号： H01L31/00

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7787 ,  H01L2221/6835 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a semiconductor layer having a principal surface on which a source electrode, a drain electrode and a gate electrode are formed and having a first through hole; an insulating film formed in contact with the semiconductor layer and having a second through hole; a first interconnection formed on the semiconductor layer through the first through hole and connected to one of the source electrode, the drain electrode and the gate electrode which is exposed in the first through hole; and a second interconnection formed on the insulating film through the second through hole and connected to another of the source electrode, the drain electrode and the gate electrode which is exposed in the second through hole. The first interconnection and the second interconnection face each other and form a microstrip line.

摘要翻译： 半导体集成电路器件包括：半导体层，其主表面上形成有源电极，漏电极和栅电极，并具有第一通孔; 形成为与所述半导体层接触并具有第二通孔的绝缘膜; 通过所述第一通孔形成在所述半导体层上并与所述第一通孔露出的所述源电极，所述漏电极和所述栅电极之一连接的第一互连; 以及通过第二通孔形成在绝缘膜上的第二互连，并与第二通孔中露出的源电极，漏电极和栅电极中的另一个连接。 第一互连和第二互连彼此面对并形成微带线。

公开(公告)号：US07898002B2

公开(公告)日：2011-03-01

申请号：US11890480

申请日：2007-08-07

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L21/337 ,  H01L21/335

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

公开(公告)号：US20110012169A1

公开(公告)日：2011-01-20

申请号：US12933283

申请日：2009-02-02

申请人： Toshiyuki Takizawa ,  Tetsuzo Ueda ,  Manabu Usuda

发明人： Toshiyuki Takizawa ,  Tetsuzo Ueda ,  Manabu Usuda

IPC分类号： H01L33/32

CPC分类号： H01L21/02433 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/08 ,  H01L33/20 ,  H01L33/24 ,  H01L2933/0016 ,  H01S5/34333

摘要： A nitride semiconductor light-emitting device includes a substrate (101) made of silicon, a mask film (102) made of silicon oxide, formed on a principal surface of the substrate (101), and having at least one opening (102a), a seed layer (104) made of GaN selectively formed on the substrate (101) in the opening (102a), an LEG layer (105) formed on a side surface of the seed layer (104), and an n-type GaN layer (106), an active layer (107), and a p-type GaN layer (108) which are formed on the LEG layer (105). The LEG layer (105) is formed by crystal growth using an organic nitrogen material as a nitrogen source.

摘要翻译： 一种氮化物半导体发光器件，包括由硅制成的衬底（101），形成在衬底（101）的主表面上的由氧化硅制成的掩模膜（102），并具有至少一个开口（102a）， 在所述开口（102a）中的所述基板（101）上选择性地形成有GaN的种子层（104），形成在所述籽晶层（104）的侧面上的LEG层（105）和n型GaN层 （106），有源层（107）和形成在LEG层（105）上的p型GaN层（108）。 使用有机氮材料作为氮源，通过晶体生长形成LEG层（105）。

公开(公告)号：US07863649B2

公开(公告)日：2011-01-04

申请号：US12331668

申请日：2008-12-10

申请人： Masahiro Hikita ,  Tetsuzo Ueda

发明人： Masahiro Hikita ,  Tetsuzo Ueda

IPC分类号： H01L29/739

CPC分类号： H01L29/2003 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/808

摘要： A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.

摘要翻译： 氮化物半导体器件包括：顺序地在衬底上形成的第一至第三氮化物半导体层。 第二氮化物半导体层的带隙能量大于第一氮化物半导体层的带隙能量。 第三氮化物半导体层具有开口。 形成p型第四氮化物半导体层，使得开口被填充。 在第四氮化物半导体层上形成栅电极。

公开(公告)号：US20100327293A1

公开(公告)日：2010-12-30

申请号：US12880704

申请日：2010-09-13

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/20

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。