公开(公告)号：US07098718B2

公开(公告)日：2006-08-29

申请号：US11009377

申请日：2004-12-10

申请人： Zibing Yang ,  Todd A. Hinck ,  Howard I. Cohen ,  Allyn Hubbard

发明人： Zibing Yang ,  Todd A. Hinck ,  Howard I. Cohen ,  Allyn Hubbard

IPC分类号： H06G7/19

CPC分类号： H03F3/45475 ,  G06G7/18 ,  H03F3/45183 ,  H03F2203/45018 ,  H03F2203/45026 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45356 ,  H03F2203/45466 ,  H03G5/02 ,  H03H11/1291

摘要： A tunable current mode integrator for low-frequency continuous-time filters that requires a reduced amount of area when implemented in an integrated circuit (IC). The integrator includes input and output transistors, and cross-coupled current mirrors, integration capacitors, and operational transconductance amplifiers (OTAs) that form a feedback structure with the input transistors. Input currents are converted to small current swings within the OTAs, and are subsequently integrated by the capacitors. Resulting integrated voltages are converted to output currents by the output transistors.

摘要翻译： 用于低频连续时间滤波器的可调谐电流模式积分器，当在集成电路（IC）中实现时，需要减少面积的面积。 积分器包括与输入晶体管形成反馈结构的输入和输出晶体管以及交叉耦合电流镜，积分电容和运算跨导放大器（OTA）。 输入电流转换为OTA内的小电流摆幅，随后由电容器集成。 所产生的积分电压由输出晶体管转换为输出电流。

公开(公告)号：US09536863B2

公开(公告)日：2017-01-03

申请号：US13994919

申请日：2011-12-22

申请人： Todd A. Hinck ,  Zuoguo Wu ,  Aaron Martin ,  Andrew W. Martwick ,  John B. Halbert

发明人： Todd A. Hinck ,  Zuoguo Wu ,  Aaron Martin ,  Andrew W. Martwick ,  John B. Halbert

IPC分类号： G06F13/12 ,  G06F13/38 ,  H01L25/065 ,  H04B1/40 ,  H01L23/538 ,  H01L23/48 ,  H01L23/66 ,  H01L25/11

CPC分类号： H01L25/0655 ,  G06F13/385 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/66 ,  H01L25/115 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H04B1/40 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2224/0401

摘要： Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

摘要翻译： 用于互连集成电路管芯的装置。 第一组单端发射机电路包括在第一裸片上。 发射机电路阻抗匹配，无均衡。 第一组单端接收器电路包括在第二管芯上。 接收器电路没有终端，没有均衡。 导电线耦合在第一组发射器电路和第一组接收器电路之间。 导线的长度相匹配。 第一芯片，第一组单端发射机电路，第二芯片，第一组单端接收器电路和导线布置在第一封装内。 第一组芯片包括第二组单端发射机电路。 发射机电路阻抗匹配，无均衡。 根据数据总线反转（DBI）方案发送从第二组发射机电路发送的数据。 第三组裸片包括第二组单端接收机电路。 接收器电路具有端接。 导电线耦合在第二组发射器电路和第二组接收器电路之间。 导线的长度匹配，第二组接收器电路设置在第二封装内。

公开(公告)号：US20140085791A1

公开(公告)日：2014-03-27

申请号：US13629357

申请日：2012-09-27

申请人： TODD A. HINCK

发明人： TODD A. HINCK

IPC分类号： H04B1/40 ,  G06F1/16

CPC分类号： H04B1/40 ,  G06F1/10 ,  G06F1/1637 ,  G06F1/3203

摘要： An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

摘要翻译： 一个封装接口。 第一组第一组单端发射机电路。 发射机电路阻抗匹配，无均衡。 第二组芯片上的第一组单端接收器电路。 接收器电路没有终端，没有均衡。 多条导线耦合第一组发射机电路和第一组接收机电路。 多条导线的长度相匹配。

公开(公告)号：US20130313709A1

公开(公告)日：2013-11-28

申请号：US13994919

申请日：2011-12-22

申请人： Todd A. Hinck ,  Zuoguo Wu ,  Aaron Martin ,  Andrew W. Martwick ,  John B. Halbert

发明人： Todd A. Hinck ,  Zuoguo Wu ,  Aaron Martin ,  Andrew W. Martwick ,  John B. Halbert

IPC分类号： H01L25/065

CPC分类号： H01L25/0655 ,  G06F13/385 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/66 ,  H01L25/115 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H04B1/40 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2224/0401

摘要： Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

摘要翻译： 用于互连集成电路管芯的装置。 第一组单端发射机电路包括在第一裸片上。 发射机电路阻抗匹配，无均衡。 第一组单端接收器电路包括在第二管芯上。 接收器电路没有终端，没有均衡。 导电线耦合在第一组发射器电路和第一组接收器电路之间。 导线的长度相匹配。 第一芯片，第一组单端发射机电路，第二芯片，第一组单端接收器电路和导线布置在第一封装内。 第一组芯片包括第二组单端发射机电路。 发射机电路阻抗匹配，无均衡。 根据数据总线反转（DBI）方案发送从第二组发射机电路发送的数据。 第三组裸片包括第二组单端接收机电路。 接收器电路具有端接。 导电线耦合在第二组发射器电路和第二组接收器电路之间。 导线的长度匹配，第二组接收器电路设置在第二封装内。