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    Apparatus for decimal multiplication
    1.
    发明授权
    Apparatus for decimal multiplication 失效
    十进制乘法装置

    公开(公告)号：US4677583A

    公开(公告)日：1987-06-30

    申请号：US625131

    申请日：1984-06-27

    申请人： Toru Ohtsuki ,  Yoshio Oshima ,  Sako Ishikawa ,  Hideaki Yabe ,  Masaharu Fukuta

    发明人： Toru Ohtsuki ,  Yoshio Oshima ,  Sako Ishikawa ,  Hideaki Yabe ,  Masaharu Fukuta

    IPC分类号： G06F7/496 ,  G06F7/491 ,  G06F7/506 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527

    CPC分类号： G06F7/4915

    摘要： An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

    摘要翻译： 用于十进制乘法的装置将二进制编码十进制（BCD）的乘法器分成多个组，生成多个部分乘积乘以BCD的被乘数和连续循环的多组乘法器，并将它们添加到中间乘积 先前产生的部分产品的总和。 部分乘积和中间乘积的加法由进位保存加法器进行。 在第一个循环中，将中间产品设置为零，并且将中间产品和部分产品中的任一个的每个数字加到6上，并且部分产品和中间产品的添加由 连续循环中的进位保存加法器循环。 在最后一个循环中，进位保存加法器的和和进位由全加器相加，根据全加器各位的进位转移的存在，对每个数位进行6减，结果值为 输出为乘法结果。

    Multiplication device using multiple-input adder
    2.
    发明授权
    Multiplication device using multiple-input adder 失效
    乘法器使用多输入加法器

    公开(公告)号：US4543641A

    公开(公告)日：1985-09-24

    申请号：US461257

    申请日：1983-01-26

    申请人： Masaharu Fukuta ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki

    发明人： Masaharu Fukuta ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki

    IPC分类号： G06F7/53 ,  G06F7/491 ,  G06F7/496 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527

    CPC分类号： G06F7/4915

    摘要： A multiplier device comprising hold means for holding the result of addition, block product means for producing k block products each having 2n bits, where n is an integer equal to or greater than 2, the k block products being formed by multiplying each block by n bits, k blocks being obtained by dividing a multiplicand at intervals of n bits from the least significant bit of the multiplicand, and adder means for adding two groups of block products to the output of the hold means, the two groups of block products consisting of alternate block products out of the k block products from the block product means.

    摘要翻译： 一种乘法器装置，包括用于保持加法结果的保持装置，用于产生每个具有2n位的k个块产物的块产生装置，其中n是等于或大于2的整数，所述k个块产物通过将每个块乘以n 比特，k个块通过以被乘数的最低有效位的n比特的间隔划分被乘数而获得，以及加法器装置，用于将两组块产物加到保持装置的输出，两组块产物由 替代块产品从块产品中获取块产品的手段。

    Binary coded decimal number division apparatus
    3.
    发明授权
    Binary coded decimal number division apparatus 失效
    二进制编码十进制数分割装置

    公开(公告)号：US4603397A

    公开(公告)日：1986-07-29

    申请号：US462423

    申请日：1983-01-31

    申请人： Toru Ohtsuki ,  Yoshio Oshima ,  Sako Ishikawa ,  Masaharu Fukuta

    发明人： Toru Ohtsuki ,  Yoshio Oshima ,  Sako Ishikawa ,  Masaharu Fukuta

    IPC分类号： G06F7/491 ,  G06F7/493 ,  G06F7/496 ,  G06F7/508 ,  G06F7/52

    CPC分类号： G06F7/4917

    摘要： In preparation of addresses of a quotient prediction table used in a binary coded decimal number division scheme with predetermined bits of a dividend and a divisor in binary coded decimal representation, the addresses are modified with the redundant bits. The absolute bit number for the addresses is thus decreased, whereby data quantity and hence capacity of RAM required for implementing the quotient prediction table can be significantly reduced, while satisfactory function of the quotient prediction table being assured. The apparatus for the binary coded decimal number division is implemented inexpensively in a small size.

    摘要翻译： 在用二进制编码的十进制数分割方案中使用的商数预测表的地址和二进制编码十进制表示中的除数的除数和除数的二进制编码的十进制数分割方案中，地址被修改。 因此，地址的绝对位数减少，从而可以显着地减少用于实现商预测表所需的RAM的数据量和因此的容量，同时确保商预测表的令人满意的功能。 用于二进制编码的十进制数除法的装置以小尺寸廉价地实现。

    Binary coded decimal number division apparatus
    4.
    发明授权
    Binary coded decimal number division apparatus 失效
    二进制编码十进制数分割装置

    公开(公告)号：US4635220A

    公开(公告)日：1987-01-06

    申请号：US549809

    申请日：1983-11-08

    申请人： Hideaki Yabe ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki ,  Masaharu Fukuta

    发明人： Hideaki Yabe ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki ,  Masaharu Fukuta

    IPC分类号： G06F7/491 ,  G06F7/493 ,  G06F7/496 ,  G06F7/52

    CPC分类号： G06F7/4917

    摘要： A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit. With this arrangement, three of the four bits of the predicted quotient of one digit read out from the quotient prediction table can be used directly as the selection signal for selecting the relevant divisor multiple register.

    摘要翻译： 二进制编码十进制数分割装置，其中以二进制编码十进制表示的商以逐个数字为基础通过使用商预测表和一组多值寄存器来确定，并且其中从 商预测表在预测商正确的情况下完整使用，否则预测商减1，其中存储在商预测表中的值与冗余位一起预先修改为（0110）2至（1111）2 二进制编码十进制表示。 通过使用修改的预测商的四位中的三位来选择多值寄存器，而在商确定时，从商预测表的输出值中减去用于修改的值，从而导出一个预测商的预测商 数字。 利用这种布置，从商预测表读出的一位数的预测商的四位中的三位可以直接用作选择相关除数多寄存器的选择信号。

    Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (STO) while using space registers as storage devices for a data processing system
    6.
    发明授权
    Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (STO) while using space registers as storage devices for a data processing system 失效
    在使用空间寄存器作为数据处理系统的存储设备时，使用/比较包含空格地址和原始地址（STO）的地址的翻译对的多个虚拟寻址

    公开(公告)号：US5226132A

    公开(公告)日：1993-07-06

    申请号：US413444

    申请日：1989-09-27

    申请人： Michitaka Yamamoto ,  Toshinori Kuwabara ,  Yoshio Oshima ,  Yasutaka Yamada

    发明人： Michitaka Yamamoto ,  Toshinori Kuwabara ,  Yoshio Oshima ,  Yasutaka Yamada

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0292

    摘要： Instead of translation from a space address to a segment table origin address (STO) by an ordinary instruction, translation to the STO is done by a space base register modify instruction which uses an instruction to modify the content of the space register, and the result thereof is used for the operand address calculation of the instruction to the operand data fetching. The present system eliminates the need for additionally providing for hardware of an operand fetch unit hardware for the translation from the space address to the STO, memory for storing translation pairs of the space addresses and the STO's and the table look-up of the translation pairs. Thus, degradation of performance is minimized with less hardware.

    摘要翻译： 代替通过普通指令从空间地址到段表原点地址（STO）的转换，通过使用修改空间寄存器的内容的指令的空间基地址寄存器修改指令来进行到STO的转换，结果 用于对操作数数据取出指令的操作数地址计算。 本系统不需要另外提供用于从空间地址到STO的转换的操作数获取单元硬件的硬件，用于存储空间地址和STO的转换对的存储器以及翻译对的表查找 。 因此，通过较少的硬件使性能下降最小化。

    System using selected logical processor identification based upon a select address for accessing corresponding partition blocks of the main memory
    8.
    发明授权
    System using selected logical processor identification based upon a select address for accessing corresponding partition blocks of the main memory 失效
    基于用于访问主存储器的对应分区块的选择地址来使用所选择的逻辑处理器标识的系统

    公开(公告)号：US5210844A

    公开(公告)日：1993-05-11

    申请号：US412508

    申请日：1989-09-26

    申请人： Nobuyuki Shimura ,  Kazuo Hibi ,  Yoshio Oshima

    发明人： Nobuyuki Shimura ,  Kazuo Hibi ,  Yoshio Oshima

    IPC分类号： G06F12/14 ,  G06F9/46 ,  G06F12/02 ,  G06F21/24

    CPC分类号： G06F9/468

    摘要： An information processing apparatus having at least one processor and a main storage, accessed by the processor, and capable of providing a plurality of logical information processing apparatus by logically partitioning the information processing apparatus. The information processing apparatus includes a main storage partitioned into a plurality of memory areas, each of the memory areas corresponding to one of the plurality of logical information processing apparatus. The information processing apparatus further includes a first storage unit for storing identification information for each of the memory areas identifying the logical information processing apparatus allocated to each memory and a read unit for reading the identification information from the first storage unit when the main storage is to be accessed by one of the plurality of logical information processing apparatus. Each of the plurality of logical information processing apparatus possesses a unique identification information. The information processing apparatus further includes a comparison unit for comparing the identification information read by the read unit with the identification information of the one logical information processing apparatus which accesses the main storage and a unit for determining if the access to the main storage is allowed, in accordance with the comparison result of the comparison unit. Access by the one logical information processing apparatus is canceled if the determining unit determines the access is not allowable.

    摘要翻译： 一种信息处理装置，具有由处理器访问的至少一个处理器和主存储器，并且能够通过逻辑地分割信息处理装置来提供多个逻辑信息处理装置。 信息处理装置包括：分割成多个存储区域的主存储器，每个存储区域对应于多个逻辑信息处理装置之一。 信息处理装置还包括：第一存储单元，用于存储识别分配给每个存储器的逻辑信息处理装置的每个存储区域的识别信息;以及读取单元，用于当主存储器被写入时从第一存储单元读取识别信息 由多个逻辑信息处理装置中的一个访问。 多个逻辑信息处理装置中的每一个具有唯一的识别信息。 信息处理装置还包括：比较单元，用于将由读取单元读取的识别信息与访问主存储器的一个逻辑信息处理设备的识别信息进行比较;以及单元，用于确定是否允许访问主存储器; 按照比较单位的比较结果。 如果确定单元确定访问不可允许，则由一个逻辑信息处理设备的访问被取消。