公开(公告)号：US08657496B2

公开(公告)日：2014-02-25

申请号：US12630544

申请日：2009-12-03

申请人： Yasuhiro Takeda ,  Kenji Washida ,  Takahiro Koyama ,  Junichi Hashimoto ,  Matsutarou Ono ,  Yasuharu Takada ,  Toshihiko Mori ,  Moritoshi Oguni

发明人： Yasuhiro Takeda ,  Kenji Washida ,  Takahiro Koyama ,  Junichi Hashimoto ,  Matsutarou Ono ,  Yasuharu Takada ,  Toshihiko Mori ,  Moritoshi Oguni

IPC分类号： B65D33/00 ,  B65D65/26

CPC分类号： B65D75/5883 ,  B65D2575/583

摘要： A spout member including a base portion which is fixed to a bag body, a cylindrical portion which protrudes upward from the base portion, and a sealing portion which seals a front end of the cylindrical portion through a breakable thin portion is disposed between two sheets of film forming the bag body. A sealing chamber accommodating the cylindrical portion and the sealing portion is opened by tearing the two sheets of film along an opening assisting line. An opening assisting plate protruding to at least one of a left side and a right side of the sealing portion is disposed above the opening assisting line. A sandwiching reinforcement seal portion for reinforcing the two sheets of film by sealing inner surfaces thereof is provided between the opening assisting plate and the opening assisting line.

摘要翻译： 一种喷嘴构件，其包括固定到袋体的基部，从基部向上突出的圆柱形部分和通过可破裂的薄部分将圆柱形部分的前端密封的密封部分设置在两片 胶片成型袋体。 容纳圆筒部和密封部的密封室通过沿着打开辅助线撕裂两片胶片而打开。 在密封部的左侧和右侧的至少一方突出的开启辅助板设置在开启辅助线的上方。 在开启辅助板和开启辅助线之间设置用于通过密封其内表面来加强两片薄膜的夹层加强密封部。

公开(公告)号：US20110293202A1

公开(公告)日：2011-12-01

申请号：US13061772

申请日：2009-09-01

申请人： Yasuhiro Takeda ,  Kenji Washida ,  Takahiro Koyama ,  Tetsushi Mori ,  Yasuharu Takada ,  Moritoshi Oguni ,  Hirotaka Ikeda ,  Toshihiko Mori ,  Matsutarou Ono

发明人： Yasuhiro Takeda ,  Kenji Washida ,  Takahiro Koyama ,  Tetsushi Mori ,  Yasuharu Takada ,  Moritoshi Oguni ,  Hirotaka Ikeda ,  Toshihiko Mori ,  Matsutarou Ono

IPC分类号： B65D33/06 ,  B65D41/32

CPC分类号： B65D33/1691 ,  B65D33/2533 ,  B65D75/566 ,  B65D75/5883

摘要： It is aimed to provide a spout member and a packaging bag using the spout member which have excellent handling property and hygiene management performance at the time of supplying water or the like from the outside before and during use such as administration of water and medicine, in which a closure means for freely opening and closing an aperture formed by cutting off parts of peripheral portions of sealed film pieces is protected from a contained content at the time of storage or transportation and which have excellent protecting property even when an inner pressure acts in the packaging bag, excellent contamination preventing property until a spout is opened and excellent contamination preventing property and handling property after opening.In a packaging bag formed by sealing peripheral portions of a plurality of film pieces and including an inlet portion and a spout portion at the peripheral portions, the inlet portion is opened as an inlet port by cutting off parts of the peripheral portions of the sealed film pieces to form an aperture by an unsealed portion, at least two holes are formed at the opposite sides of a part which becomes the inlet port at the peripheral portions near the inlet portion, and the holes serve as a suspension means for enabling the packaging bag to be suspended and a finger holding means. An operable and closable closure means including first and second members engageable with each other is formed by bonding an upper part of a first base member including the first member and an upper part of a second base member including the second member respectively to inner sides of the film pieces forming the aperture and facing each other, and a bottom end portion of one base member is formed to be longer than that of the other base member and bonded to the other film piece opposite thereto by an easily peelable seal, thereby forming an easily peelable portion which is peeled open to open the aperture at the time of opening. A spout member is provided with a spout portion including a base portion and a cylindrical portion projecting from the base portion, a sealing portion for sealing a tip portion of the cylindrical portion via a tearable weakened portion, and a cap portion. The weakened portion is torn by turning the cap portion to separate the sealing portion and the cap portion from the spout portion and simultaneously open the tip portion of the cylindrical portion, thereby forming a spout. The cap portion is shaped to cover the entire cylindrical portion, and the cap portion and the spout portion include a locking mechanism capable of locking the cap portion to the spout portion.

公开(公告)号：US06292408B1

公开(公告)日：2001-09-18

申请号：US09479236

申请日：2000-01-07

申请人： Shoichiro Kawashima ,  Toshihiko Mori ,  Makoto Hamaminato

发明人： Shoichiro Kawashima ,  Toshihiko Mori ,  Makoto Hamaminato

IPC分类号： G11C700

CPC分类号： G11C11/419

摘要： A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line. The second transistor has a current input terminal connected to the power source line and a current output terminal connected to the second bit line. A transistor drive circuit drives, during a write recovery period, one of the first transistor and the second transistor which is connected to one of the first bit line and the second bit line which is set to a lower potential.

摘要翻译： 一种半导体存储器件，其可以通过减小用于提高构成写恢复电路的位线的晶体管的栅极电容的充电和放电电流来降低功耗。 一对第一和第二位线连接到存储单元。 根据写入数据，在写入周期期间第一和第二位线之一的电位降低。 第一加载元件连接在电源线和第一位线之间。 电源线提供正电源电压。 第二加载元件连接在电源线和第二位线之间。 提供第一晶体管用于提升第一位线。 第一晶体管具有连接到电源线的电流输入端子和连接到第一位线的电流输出端子。 第二晶体管用于提升第二位线。 第二晶体管具有连接到电源线的电流输入端和连接到第二位线的电流输出端。 晶体管驱动电路在写恢复期间驱动第一晶体管和第二晶体管中的一个连接到被设置为较低电位的第一位线和第二位线之一。

公开(公告)号：US5905297A

公开(公告)日：1999-05-18

申请号：US936629

申请日：1997-09-23

申请人： Toshihiko Mori ,  Yoshiaki Nakata

发明人： Toshihiko Mori ,  Yoshiaki Nakata

IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/203 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8252 ,  H01L29/737 ,  H01L21/437 ,  H01L29/04

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  H01L21/822 ,  H01L21/8252 ,  Y10S148/041 ,  Y10S148/169 ,  Y10S438/973

摘要： A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the off-substrate and made of semiconductor material, the wiring layer including a plurality of conductive stripe regions and high resistance strip regions disposed in a stripe pattern, each stripe region extending in a direction parallel with the steps, and the conductive stripe regions and the high resistance stripe regions both having lattice structures identical to those of underlying surfaces; and semiconductor elements formed on the wiring layer and electrically connected to the conductive stripe regions, the semiconductor elements including semiconductor regions with lattice structures identical to those of the conductive stripe regions. Technologies of manufacturing a semiconductor element on a semiconductor substrate capable of reducing the number of fine pattern fabrication processes by photolithography or capable of dispensing with these processes.

摘要翻译： 一种半导体集成电路器件，包括：具有多个台阶的半导体表面的离型基板，每个台阶具有一个单层的高度并沿一个方向延伸; 布线层，其形成在所述离型基板的半导体表面上，由半导体材料制成，所述布线层包括多个导电条纹区域和设置在条纹图案中的高电阻条带区域，每个条带区域沿与 步骤，并且导电条纹区域和高电阻条纹区域都具有与底层表面相同的晶格结构; 以及形成在所述布线层上并与导电条纹区电连接的半导体元件，所述半导体元件包括具有与所述导电条纹区域相同的格子结构的半导体区域。 在半导体衬底上制造半导体元件的技术，其能够通过光刻法减少精细图案制造工艺的数量或能够分配这些工艺。

公开(公告)号：US5864821A

公开(公告)日：1999-01-26

申请号：US622630

申请日：1996-03-27

申请人： Naofumi Hosoda ,  Masato Tamaki ,  Toshihiko Mori ,  Masafumi Itabashi ,  Mitsuko Yoshimoto

发明人： Naofumi Hosoda ,  Masato Tamaki ,  Toshihiko Mori ,  Masafumi Itabashi ,  Mitsuko Yoshimoto

IPC分类号： G06F13/00 ,  G06F19/00 ,  G06Q10/10 ,  G06Q99/00 ,  G06F155/00

CPC分类号： G06Q99/00 ,  G06Q10/0631

摘要： Even if undecided portion is contained in the data which is necessary for a series of business processings, necessary data is transmitted to the business processing section which wants to confirm the necessary data without carrying out the destination specifying operation. When inputting data from the business processing section in charge of input, parameters representing the degrees of decision are input together with the data and are stored in a database which is common to the business processing sections, the progress stage of a series of business processings is judged on the basis of a progress stage definition table in which the relation between the input situation of the data items and the parameters, and the progress stages of the series of business processings is defined. The data items which are to be transmitted in the progress stages and the transmission destinations are judged based on a transmission destination definition table in which the relation among the progress stages of the series of business processings, the data items as objects of the transmission and the transmission destinations is defined. The data of interest is fetched from the common database, and is transmitted to a data input/output unit of the business processing section as the transmission destination obtained by the judgement results.

摘要翻译： 即使在一系列业务处理中所需要的数据中包含未决定的部分，在不执行目的地指定操作的情况下，将必要的数据发送到要确认所需数据的业务处理部。 当从负责输入的业务处理部分输入数据时，表示决策程度的参数与数据一起输入并存储在业务处理部分共同的数据库中，一系列业务处理的进度阶段是 根据进度阶段定义表判断数据项的输入情况与参数之间的关系以及业务处理系列的进度阶段的定义。 在进度阶段和发送目的地中要发送的数据项是基于发送目的地定义表来判断的，其中，一系列业务处理的进度阶段之间的关系，作为传输对象的数据项和 传输目的地被定义。 感兴趣的数据从通用数据库中取出，并作为通过判断结果得到的发送目的地被发送到业务处理部的数据输入/输出部。

公开(公告)号：US5864152A

公开(公告)日：1999-01-26

申请号：US637182

申请日：1996-04-24

申请人： Toshihiko Mori

发明人： Toshihiko Mori

IPC分类号： G11C11/411 ,  G11C11/34 ,  G11C11/40 ,  H01L21/8229 ,  H01L27/102 ,  H01L29/08 ,  H01L29/737 ,  H01L29/201

CPC分类号： H01L27/102 ,  G11C11/34 ,  G11C11/40 ,  H01L29/0813 ,  H01L29/0817 ,  H01L29/7371

摘要： A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The first emitter of each transistor is connected to a corresponding one of the ground lines. The second emitter is connected to a corresponding one of the word lines. The collector is connected to a corresponding one of the bit lines. Each of the memory cells has a small number of elements and requires only a small area.

摘要翻译： 半导体存储器具有位线，字线，接地线和存储单元。 位线与字线和地线相交，分别形成存储单元布置的交点。 每个存储单元由双发射极晶体管组成。 该晶体管具有集电极，第一发射极和第二发射极。 晶体管的每个基极 - 发射极结具有N形的负差分电流 - 电压特性，其在峰值电流之前显示相对小的增益和在谷值电流之后具有相对较大的增益。 每个晶体管的第一发射极连接到对应的一条接地线。 第二发射器连接到相应的字线之一。 集电极连接到相应的一个位线。 每个存储器单元具有少量的元件，并且仅需要小的面积。

公开(公告)号：US5019185A

公开(公告)日：1991-05-28

申请号：US436737

申请日：1989-11-15

申请人： Takashi Nakajima ,  Kenji Kubozono ,  Toshihiko Mori ,  Takefumi Ito ,  Kimio Hashitsume ,  Shinichi Iwase

发明人： Takashi Nakajima ,  Kenji Kubozono ,  Toshihiko Mori ,  Takefumi Ito ,  Kimio Hashitsume ,  Shinichi Iwase

IPC分类号： C22C9/06 ,  C22F1/00 ,  C22F1/08

CPC分类号： C22F1/08 ,  C22C9/06

摘要： A high strength Cu-Ni-Sn alloy, comprising 3-25% Ni, 3-9% Sn, 0.05-1.5% Mn, balance Cu, is heated to a temperature of 800.degree. C. or above in a single-phase region. This heat treatment is followed by quenching and subsequent heating at a temperature range of 600.degree.-770.degree. C. in a two-phase region, followed by quenching and a finishing process with a ratio of 0-60%. Thereafter, the processed alloy is subjected to a final heat-treatment at a temperature of 350.degree.-500.degree. C.

摘要翻译： 将包含3-25％Ni，3-9％Sn，0.05-1.5％Mn余量Cu的高强度Cu-Ni-Sn合金在单相区域中加热到800℃以上的温度 。 进行该热处理后，在600℃-770℃的温度范围内淬火，随后在两相区域中进行加热，然后以0-60％的比例淬火和精加工。 然后，将处理后的合金在350〜-500℃的温度下进行最终的热处理。

公开(公告)号：US20130217556A1

公开(公告)日：2013-08-22

申请号：US13882081

申请日：2010-12-16

申请人： Toshihiko Mori ,  Tomoko Kubota ,  Yasuharu Takada

发明人： Toshihiko Mori ,  Tomoko Kubota ,  Yasuharu Takada

IPC分类号： B31B19/00 ,  B65D35/10 ,  B29D22/00

CPC分类号： B65D75/5822 ,  B29D22/00 ,  B29D22/003 ,  B29K2995/0041 ,  B29L2009/00 ,  B31B70/252 ,  B31B70/857 ,  B31B2155/00 ,  B31B2155/002 ,  B31B2160/20 ,  B65D75/008

摘要： A manufacturing method of a package bag (10) according to the present invention includes: a cured portion forming step of forming a cured portion (15a, 15b) on at least one side of a forming position of a rib (14) by crystallizing at least a portion of a resin constituting a film (11) by heating and cooling the film (11); and a rib forming step of forming a rib (14) by pressing the film (11) using concave and convex molds. According to the present invention, it is possible to maintain an opening state of a spout (12). Further, since additional material is not required, it is possible to suppress increase in the thickness of the package bag (10) and to reduce the bulkiness of the package bags.

摘要翻译： 根据本发明的包装袋（10）的制造方法包括：固化部分形成步骤，通过在肋（14）的成形位置的至少一个侧面上结晶而形成固化部分（15a，15b） 通过加热和冷却膜（11），构成膜（11）的树脂的至少一部分; 以及通过使用凹凸模压制薄膜（11）来形成肋（14）的肋形成步骤。 根据本发明，可以保持喷口（12）的打开状态。 此外，由于不需要附加材料，因此可以抑制包装袋（10）的厚度增加并减小包装袋的蓬松性。

公开(公告)号：US08344456B2

公开(公告)日：2013-01-01

申请号：US12606438

申请日：2009-10-27

申请人： Masahito Arakawa ,  Toshihiko Mori

发明人： Masahito Arakawa ,  Toshihiko Mori

IPC分类号： H01L23/60

CPC分类号： H01L23/60 ,  H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied.

摘要翻译： 一种ESD保护电路，包括：设置在第一电源布线和第一接地布线之间的第一静电放电保护电路; 设置在第二电源布线和第二接地布线之间的第二ESD保护电路; 设置在所述第一接地布线和所述第二接地布线之间的第三ESD保护电路; 耦合到第一电源布线并设置在耦合到第一接地布线的第一CMOS电路和第一电源布线之间的PMOS晶体管，第一CMOS电路接收来自第一内部电路的信号，并将信号输出到第一节点 ; 设置在所述第一节点和所述第一接地布线之间的NMOS晶体管; 以及在正常操作期间使PMOS晶体管导通和NMOS晶体管不导通的ESD检测电路，并且当施加ESD时使得PMOS晶体管不导通并且NMOS晶体管导通。

公开(公告)号：US20120013362A1

公开(公告)日：2012-01-19

申请号：US13181825

申请日：2011-07-13

申请人： Tetsuya HIROSE ,  Yuji OSAKI ,  Toshihiko MORI

发明人： Tetsuya HIROSE ,  Yuji OSAKI ,  Toshihiko MORI

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal.

摘要翻译： 提供电平转换器电路，用于将具有第一信号电平的数字信号的输入信号转换为具有高于第一信号电平的第二信号电平的输出信号。 放大器电路放大输入信号并输出​​放大的输出信号，并且电流发生器电路在输入信号的信号电平改变时产生对应于流过放大器电路的工作电流的控制电流。 电流检测器电路检测所产生的控制电流，并且控制放大器电路的工作电流对应于检测到的控制电流。 电流发生器电路包括插入电流检测器电路和地之间的串联连接的第一和第二nMOS晶体管。 第一nMOS晶体管响应于输入信号而工作，并且第二nMOS晶体管响应输入信号的反相信号而工作。