公开(公告)号：US07218132B2

公开(公告)日：2007-05-15

申请号：US11290077

申请日：2005-11-30

申请人： Anand T. Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

发明人： Anand T. Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

公开(公告)号：US5582770A

公开(公告)日：1996-12-10

申请号：US255497

申请日：1994-06-08

申请人： Edward F. Chu ,  Nelson H. Thein ,  Vijay Reddy ,  Daniel A. Chandler

发明人： Edward F. Chu ,  Nelson H. Thein ,  Vijay Reddy ,  Daniel A. Chandler

IPC分类号： C08K3/00 ,  C08K3/04 ,  C08L23/04 ,  C08L23/06 ,  C08L23/08 ,  H01B1/12 ,  H01B1/20 ,  H01B1/22 ,  H01B1/24 ,  H01C7/02 ,  H01M2/34 ,  H01M4/66 ,  H01M6/50 ,  H01M10/30 ,  H01M10/42 ,  H01M10/48 ,  C08L33/08

CPC分类号： H01M10/48 ,  C08L23/0869 ,  H01B1/12 ,  H01B1/20 ,  H01B1/22 ,  H01B1/24 ,  H01C7/027 ,  H01M10/42 ,  H01M10/425 ,  H01M2/348 ,  H01M4/668 ,  C08L2203/202 ,  C08L23/06 ,  H01M2200/106 ,  H01M2200/20 ,  Y10T428/31504

摘要： A conductive polymer composition containing a particulate conductive filler dispersed in a polymeric component. The polymeric component comprises a first polymer which (i) is present in an amount 25 to 75% by weight of the total polymeric component, and (ii) is polyethylene, and a second polymer which (i) is present in an amount 25 to 75% by weight of the total polymeric component, and (ii) comprises units derived from a first monomer which is ethylene and a second monomer which is an alkyl acrylate having the formula --CH.sub.2 .dbd.CHCOOC.sub.m H.sub.2m+1 --, where m is at least 4. The resulting composition is useful in preparing electrical devices, e.g. circuit protection devices, which have lower resistivities, higher PTC anomalies, and better thermal and electrical stability than devices comprising conventional conductive polymer compositions.

摘要翻译： 一种含有分散在聚合物组分中的颗粒状导电填料的导电聚合物组合物。 聚合物组分包含第一聚合物，其中（i）以总聚合物组分的25至75重量％的量存在，和（ii）是聚乙烯，和第二聚合物，其中（i）以25至 75重量％的总聚合物组分，和（ii）包含衍生自乙烯的第一单体的单元和具有式-CH 2 = CHCOOC m H 2 m + 1的丙烯酸烷基酯的第二单体，其中m为至少4 所得组合物可用于制备电气装置，例如 电路保护装置，其具有比包含常规导电聚合物组合物的装置更低的电阻率，更高的PTC异常以及更好的热和电稳定性。

公开(公告)号：US5317061A

公开(公告)日：1994-05-31

申请号：US21827

申请日：1993-02-24

申请人： Edward F. Chu ,  Vijay Reddy ,  Robert P. Saltman

发明人： Edward F. Chu ,  Vijay Reddy ,  Robert P. Saltman

IPC分类号： C08L27/12 ,  C08L27/18 ,  C08L27/20

CPC分类号： C08L27/18 ,  C08L2205/02 ,  C08L27/12

摘要： A composition which contains 35 to 85% by weight of a copolymer of tetrafluoroethylene and hexafluoropropylene (FEP), 10 to 60% by weight of a copolymer of tetrafluoroethylene and perfluoropropylvinyl ether (PFA), and 5 to 60% by weight of melt-processable polytetrafluoroethylene (PTFE). The composition is particularly suitable for use as an insulating material on a substrate such as a resistive element in a conductive polymer heating cable. The composition has good physical properties, low creep, and low secondary crystallization, and exhibits little stress-cracking when exposed to elevated temperatures.

摘要翻译： 含有35〜85重量％的四氟乙烯和六氟丙烯（FEP）的共聚物，10〜60重量％的四氟乙烯和全氟丙基乙烯基醚（PFA）的共聚物和5〜60重量％的可熔融加工的组合物 聚四氟乙烯（PTFE）。 该组合物特别适合用作导电聚合物加热电缆中诸如电阻元件的基底上的绝缘材料。 该组合物具有良好的物理性能，低蠕变性和低二次结晶性，并且当暴露于升高的温度时表现出很小的应力开裂。

公开(公告)号：US07263455B2

公开(公告)日：2007-08-28

申请号：US11152318

申请日：2005-06-14

申请人： John Anthony Rodriguez ,  Vijay Reddy

发明人： John Anthony Rodriguez ,  Vijay Reddy

IPC分类号： H04L1/22

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

摘要： Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also disclosed provided, including measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.

摘要翻译： 提供了用于在晶片中疲劳测试铁电材料的装置，其包括片上振荡器以向形成在晶片中的铁电电容器提供双极波形，以及用于选择性地提供对铁电电容器的外部访问的开关系统。 还提供了测试方法，包括测量晶片中的铁电电容器的性能特性，使用片上振荡器向铁电电容器提供双极波形多个周期，并再次测量整数之后的性能特性 的双极波形的周期。

公开(公告)号：US07212023B2

公开(公告)日：2007-05-01

申请号：US10935375

申请日：2004-09-07

申请人： Anand T. Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

发明人： Anand T. Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

摘要翻译： 提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。 在测试期间，晶体管的漏极端子保持偏置电压。 在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。 在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

公开(公告)号：US20060049842A1

公开(公告)日：2006-03-09

申请号：US10935375

申请日：2004-09-07

申请人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

发明人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

摘要翻译： 提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。 在测试期间，晶体管的漏极端子保持偏置电压。 在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。 在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

公开(公告)号：US20050086038A1

公开(公告)日：2005-04-21

申请号：US10687796

申请日：2003-10-17

申请人： Vijay Reddy ,  Robert Pitts

发明人： Vijay Reddy ,  Robert Pitts

IPC分类号： G01R27/28 ,  G01R31/26 ,  G06F17/50 ,  H01L21/66 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L22/34

摘要： According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay elements. Each delay element operates as a delay element through the use of one or more transistors of only a first type and no transistors of the opposite type. The method further includes operating the ring oscillator and measuring the frequency resulting from the ring oscillator over time. The magnitude of an isolated degradation mechanism is determined based on a comparison of the measured frequency and an expected frequency for the ring oscillator absent degradation.

公开(公告)号：US20120156237A1

公开(公告)日：2012-06-21

申请号：US13167627

申请日：2011-06-23

申请人： JOHN YOUNG ,  ANETTE SCHNEEMANN ,  MARIANNE MANCHESTER ,  KELLY DRYDEN ,  JOHN M. MARLETT ,  DARLY JOSEPH MANAYANI ,  GODFREY JONAH ANDERSON RAINEY ,  VIJAY REDDY ,  MARC E. SILADI ,  HEATHER M. SCOBIE ,  DIANE THOMAS ,  MARK YEAGER

发明人： JOHN YOUNG ,  ANETTE SCHNEEMANN ,  MARIANNE MANCHESTER ,  KELLY DRYDEN ,  JOHN M. MARLETT ,  DARLY JOSEPH MANAYANI ,  GODFREY JONAH ANDERSON RAINEY ,  VIJAY REDDY ,  MARC E. SILADI ,  HEATHER M. SCOBIE ,  DIANE THOMAS ,  MARK YEAGER

IPC分类号： A61K39/385 ,  C07K17/02 ,  A61P31/04 ,  C07K19/00 ,  A61K38/16

CPC分类号： A61K39/07 ,  A61K2039/5256 ,  A61K2039/5258 ,  C12N2710/14143 ,  C12N2770/30023

摘要： Antitoxin and vaccine compositions based on nodavirus VLPs are provided. Anthrax antitoxin and vaccine compositions are provided. Methods of treating toxins with VLP-based antitoxins are provided. Methods of raising an immune response with immunogen decorated VLPs are provided.

摘要翻译： 提供了基于转染病毒VLP的抗毒素和疫苗组合物。 提供炭疽毒素抗毒素和疫苗组合物。 提供了使用基于VLP的抗毒素治疗毒素的方法。 提供了用免疫原装饰的VLP提高免疫应答的方法。

公开(公告)号：US20060076971A1

公开(公告)日：2006-04-13

申请号：US11290077

申请日：2005-11-30

申请人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

发明人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

公开(公告)号：US20050231997A1

公开(公告)日：2005-10-20

申请号：US11152318

申请日：2005-06-14

申请人： John Rodriguez ,  Vijay Reddy

发明人： John Rodriguez ,  Vijay Reddy

IPC分类号： G11C11/22 ,  G11C29/50 ,  H04L1/22

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

摘要： Apparatus are disclosed for fatigue testing ferroelectric material in a wafer, comprising an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also disclosed, comprising measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.

摘要翻译： 公开了用于疲劳测试晶片中的铁电材料的装置，其包括用于向形成在晶片中的铁电电容器提供双极波形的片上振荡器，以及用于选择性地提供对铁电电容器的外部访问的开关系统。 还公开了测试方法，包括测量晶片中的铁电电容器的性能特征，使用片上振荡器向铁电电容器提供双极波形多个周期，并再次测量整数倍的 双极波形的周期。