公开(公告)号：US20110175682A1

公开(公告)日：2011-07-21

申请号：US12788021

申请日：2010-05-26

申请人： Wei Zen Chen ,  Yen-Wei Lee

发明人： Wei Zen Chen ,  Yen-Wei Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/1075 ,  H03L7/16 ,  H03L2207/50

摘要： A phase-locked loop frequency synthesizer and a loop locking method thereof are provided. The phase-locked loop frequency synthesizer includes a reference route sigma-delta modulator feedback circuit, a reference phase integration circuit coupled to the output end of the reference route sigma-delta modulator feedback circuit, a phase/frequency detector coupled to the output ends of the reference and feedback phase integration circuit, a loop filter coupled to the output end of the phase/frequency detector and the input end of the reference route sigma-delta modulator feedback circuit, an oscillator coupled to the output end of the loop filter, and a feedback phase integration circuit coupled to the output end of the oscillator and the input end of the phase/frequency detector. In the phase-locked loop frequency synthesizer, the oscillator generates corresponding frequency output signals which yield the advantages of resisting noise signals, enhancing resolution, and facilitating integration.

摘要翻译： 提供了一种锁相环频率合成器及其环路锁定方法。 锁相环频率合成器包括参考路径Σ-Δ调制器反馈电路，耦合到参考路径Σ-Δ调制器反馈电路的输出端的参考相位积分电路，耦合到输出端的相位/频率检测器 参考和反馈相位积分电路，耦合到相位/频率检测器的输出端和参考路径Σ-Δ调制器反馈电路的输入端的环路滤波器，耦合到环路滤波器的输出端的振荡器，以及 耦合到振荡器的输出端和相位/频率检测器的输入端的反馈相位积分电路。 在锁相环频率合成器中，振荡器产生对应的频率输出信号，产生抗噪声信号的优点，增强分辨率，便于集成。

公开(公告)号：US07978014B2

公开(公告)日：2011-07-12

申请号：US12404588

申请日：2009-03-16

申请人： Wei-Zen Chen ,  Song-Yu Yang

发明人： Wei-Zen Chen ,  Song-Yu Yang

IPC分类号： H03L7/00

CPC分类号： H03L7/107 ,  H03L7/087 ,  H03L7/093 ,  H03L7/095

摘要： A digital PLL frequency synthesizer characterized by fast-locking and low-jitters is presented. The PLL comprises a phase detector, a controllable oscillator, a loop filter having an automatically-adjusted loop gain, a feedback phase integration circuit, and a reference phase integration circuit. Fast-locking is achieved by dynamically adjusting forward-path gain and integral-path gain according to the output of the phase detector and the output of the integral-path during phase tracking. A skew-compensated counter circuit is proposed, which incorporates an asynchronous counter, a data register and a sample phase generator and features high-speed and low-power operation.

摘要翻译： 提出了一种以快锁和低抖动为特征的数字PLL频率合成器。 PLL包括相位检测器，可控振荡器，具有自动调节的环路增益的环路滤波器，反馈相位积分电路和参考相位积分电路。 通过在相位跟踪期间根据相位检测器的输出和积分路径的输出动态调整前向增益和积分路径增益来实现快速锁定。 提出了一种偏移补偿计数器电路，其包括异步计数器，数据寄存器和采样相位发生器，并具有高速和低功耗操作。

公开(公告)号：US20080233914A1

公开(公告)日：2008-09-25

申请号：US11862290

申请日：2007-09-27

申请人： Wei-Zen Chen ,  Tai-You Lu

发明人： Wei-Zen Chen ,  Tai-You Lu

IPC分类号： H04B1/26

CPC分类号： H03D13/004 ,  H03L7/193

摘要： A method and an apparatus for frequency synthesizing are provided for a wireless communication system. In a frequency synthesizer, a phase lock loop (PLL) circuit generates a first elemental frequency based on a reference frequency and a unity frequency. A first division module then divides the first elemental frequency to generate a second elemental frequency. A second division module divides the second elemental frequency a multiple of times to generate the unity frequency and a plurality of intermediate frequencies each having an exponential ratio to the unity frequency by a power of two. A second mixer is provided to mix one of the intermediate frequencies with the unity frequency to generate a step frequency, and a first mixer mixes the step frequency with one of the first and second elemental frequencies to generate an output frequency having a variety covering all frequency bands in an Ultra-Wide-Band (UWB) spectrum.

摘要翻译： 为无线通信系统提供频率合成的方法和装置。 在频率合成器中，锁相环（PLL）电路基于参考频率和单位频率产生第一基本频率。 第一分割模块然后划分第一基本频率以产生第二基本频率。 第二分割模块将第二基本频率分割成多次，以产生单位频率和多个中频，每个频率具有与二分频率的指数比。 提供第二混频器以将中频之一与单位频率混合以产生步进频率，并且第一混频器将步进频率与第一和第二基本频率之一混合以产生具有覆盖所有频率的多种频率的输出频率 在超宽带（UWB）频谱中的频带。

公开(公告)号：US06403267B1

公开(公告)日：2002-06-11

申请号：US09489500

申请日：2000-01-21

申请人： San-De Tzu ,  Wei-Zen Chen

发明人： San-De Tzu ,  Wei-Zen Chen

IPC分类号： G03F900

CPC分类号： G03F7/70283 ,  G03F1/32

摘要： A method of forming a high transmittance attenuated phase-shifting mask, comprising the following steps. A patterned shifter blank including a patterned shifter layer, having a first variable transmittance and a first phase angle overlying a partially exposed transparent substrate is provided. The partially exposed transparent substrate is etched for a first predetermined time to form trenches therein having a predetermined depth, increasing the first variable transmittance and the first phase angle to a second variable transmittance and a second phase angle, respectively. The shifter layer is treated with an aqueous solution of NH4OH:H2O2 for a second predetermined time, increasing the second variable transmittance to a third and final, predetermined variable transmittance, and decreasing the second phase angle to a third phase angle. Whereby the third phase angle is substantially equal to the initial phase angle of said shifter layer.

摘要翻译： 一种形成高透光率衰减相移掩模的方法，包括以下步骤。 提供了一种图案化的移位器坯件，其包括具有第一可变透射率的图案化移位器层和覆盖部分暴露的透明基板的第一相位角。 将部分曝光的透明基板蚀刻第一预定时间以在其中形成具有预定深度的沟槽，分别将第一可变透射率和第一相位角增加到第二可变透射率和第二相位角。 移位层用NH 4 OH:H 2 O 2的水溶液处理第二预定时间，将第二可变透射率增加到第三和最终的预定可变透射率，并将第二相位角减小到第三相位角。 由此第三相位角基本上等于所述移位层的初始相位角。

公开(公告)号：US20130033319A1

公开(公告)日：2013-02-07

申请号：US13563352

申请日：2012-07-31

申请人： Wei-Zen CHEN ,  Chun-Pao LIN

发明人： Wei-Zen CHEN ,  Chun-Pao LIN

IPC分类号： H03F3/217 ,  H03K7/00

CPC分类号： H03F3/2173 ,  H03F1/32 ,  H03F3/217 ,  H03F2200/114 ,  H03F2203/45138 ,  H03F2203/45512 ,  H03K7/08

摘要： An amplifier circuit includes a modulation signal generating circuit, a driving stage circuit and an output stage circuit. The modulation signal generating circuit generates a pair of modulation signals according to a pair of differential input signals and a pair of clock signals. The pair of clock signals includes a first clock signal and a second clock signal having a phase difference therebetween. The driving stage circuit generates a pair of driving signals according to the pair of modulation signals. The output stage circuit generates a pair of amplified output signals according to the pair of driving signals.

摘要翻译： 放大器电路包括调制信号发生电路，驱动级电路和输出级电路。 调制信号发生电路根据一对差分输入信号和一对时钟信号产生一对调制信号。 一对时钟信号包括第一时钟信号和在它们之间具有相位差的第二时钟信号。 驱动级电路根据该对调制信号产生一对驱动信号。 输出级电路根据该对驱动信号产生一对放大的输出信号。

公开(公告)号：US08183936B2

公开(公告)日：2012-05-22

申请号：US12788021

申请日：2010-05-26

申请人： Wei Zen Chen ,  Yen-Wei Lee

发明人： Wei Zen Chen ,  Yen-Wei Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/1075 ,  H03L7/16 ,  H03L2207/50

摘要： A phase-locked loop frequency synthesizer and a loop locking method thereof are provided. The phase-locked loop frequency synthesizer includes a reference route sigma-delta modulator feedback circuit, a reference phase integration circuit coupled to the output end of the reference route sigma-delta modulator feedback circuit, a phase/frequency detector coupled to the output ends of the reference and feedback phase integration circuit, a loop filter coupled to the output end of the phase/frequency detector and the input end of the reference route sigma-delta modulator feedback circuit, an oscillator coupled to the output end of the loop filter, and a feedback phase integration circuit coupled to the output end of the oscillator and the input end of the phase/frequency detector. In the phase-locked loop frequency synthesizer, the oscillator generates corresponding frequency output signals which yield the advantages of resisting noise signals, enhancing resolution, and facilitating integration.

摘要翻译： 提供了一种锁相环频率合成器及其环路锁定方法。 锁相环频率合成器包括参考路径Σ-Δ调制器反馈电路，耦合到参考路径Σ-Δ调制器反馈电路的输出端的参考相位积分电路，耦合到输出端的相位/频率检测器 参考和反馈相位积分电路，耦合到相位/频率检测器的输出端和参考路径Σ-Δ调制器反馈电路的输入端的环路滤波器，耦合到环路滤波器的输出端的振荡器，以及 耦合到振荡器的输出端和相位/频率检测器的输入端的反馈相位积分电路。 在锁相环频率合成器中，振荡器产生对应的频率输出信号，产生抗噪声信号的优点，增强分辨率，便于集成。

公开(公告)号：US08072280B2

公开(公告)日：2011-12-06

申请号：US12552509

申请日：2009-09-02

申请人： Wei-Zen Chen ,  Chung-Yu Wu ,  Chi-Yao Yu

发明人： Wei-Zen Chen ,  Chung-Yu Wu ,  Chi-Yao Yu

IPC分类号： H03B5/08

CPC分类号： H03K3/354 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1293 ,  H03B5/1296

摘要： A voltage-controlled oscillator comprises a variable inductor, a negative impedance circuit, an operating voltage source and a ground point. The variable inductor comprises a transformer and a transistor switch, the transformer comprising a primary side coil and a secondary side coil, the primary side coil comprising a first coil and a second coil, and the secondary side coil comprising a third coil and a fourth coil. The transistor switch is connected in parallel with the primary side coil to adjust an inductance value of the variable inductor based on a gate voltage. The negative impedance circuit is connected in parallel with the secondary side coil to compensate the power consumption of the voltage-controlled oscillator during oscillation. The operating voltage source is electrically connected between the third coil and the fourth coil, and the ground point is electrically connected between the first coil and the second coil.

摘要翻译： 压控振荡器包括可变电感器，负阻抗电路，工作电压源和接地点。 可变电感器包括变压器和晶体管开关，变压器包括初级侧线圈和次级侧线圈，初级侧线圈包括第一线圈和第二线圈，次级侧线圈包括第三线圈和第四线圈 。 晶体管开关与初级侧线圈并联连接，以根据栅极电压调节可变电感器的电感值。 负阻抗电路与次级侧线圈并联连接，以补偿振荡期间压控振荡器的功耗。 工作电压源电连接在第三线圈和第四线圈之间，并且接地点电连接在第一线圈和第二线圈之间。

公开(公告)号：US20080084955A1

公开(公告)日：2008-04-10

申请号：US11544549

申请日：2006-10-10

申请人： Wei-Zen Chen ,  Chin-Yuan Wei

发明人： Wei-Zen Chen ,  Chin-Yuan Wei

IPC分类号： H03D3/24

CPC分类号： H03D13/004

摘要： The present invention discloses a fast-locked clock and data recovery circuit, which adopts a 2× oversampling technology and comprises: a multi phase-outputting phase-locked loop generating a plurality of phases θi; a phase interpolator synthesizing the obtained phases θn and θn+2 into a sampling phase Φn based on the weighting coefficient k; a phase detector detects the phase lead or lag between the input data and the sampling phase and generates an up/down signal; and a phase search engine update the weighting coefficient and modulate the sampling phase according to the up/down correction signals. Further, the present invention proposes a data recovery circuit implementing a binary search method and a 2× oversampling method, whereby the time for clock locking can be greatly reduced. Furthermore, the present invention utilizes a multi-phase time-sharing parallel sampling technology to achieve high-speed operation and low power consumption.

摘要翻译： 本发明公开了一种采用2x过采样技术的快速锁定时钟和数据恢复电路，包括：产生多个相位的多相输出锁相环; 基于所述加权系数k将所获得的相位θn和n和n + n + 2合成到采样相位Phi N n N中的相位内插器; 相位检测器检测输入数据和采样相位之间的相位超前或滞后，并产生上/下信号; 相位搜索引擎更新加权系数，并根据上/下校正信号调制采样相位。 此外，本发明提出了一种实现二进制搜索方法和2x过采样方法的数据恢复电路，从而大大减少了时钟锁定的时间。 此外，本发明利用多相分时并行采样技术实现高速运行和低功耗。

公开(公告)号：US08729965B2

公开(公告)日：2014-05-20

申请号：US13563352

申请日：2012-07-31

申请人： Wei-Zen Chen ,  Chun-Pao Lin

发明人： Wei-Zen Chen ,  Chun-Pao Lin

IPC分类号： H03F3/217 ,  H03K7/00

CPC分类号： H03F3/2173 ,  H03F1/32 ,  H03F3/217 ,  H03F2200/114 ,  H03F2203/45138 ,  H03F2203/45512 ,  H03K7/08

摘要： An amplifier circuit includes a modulation signal generating circuit, a driving stage circuit and an output stage circuit. The modulation signal generating circuit generates a pair of modulation signals according to a pair of differential input signals and a pair of clock signals. The pair of clock signals includes a first clock signal and a second clock signal having a phase difference therebetween. The driving stage circuit generates a pair of driving signals according to the pair of modulation signals. The output stage circuit generates a pair of amplified output signals according to the pair of driving signals.

摘要翻译： 放大器电路包括调制信号发生电路，驱动级电路和输出级电路。 调制信号发生电路根据一对差分输入信号和一对时钟信号产生一对调制信号。 一对时钟信号包括第一时钟信号和在它们之间具有相位差的第二时钟信号。 驱动级电路根据该对调制信号产生一对驱动信号。 输出级电路根据该对驱动信号产生一对放大的输出信号。

公开(公告)号：US20080231372A1

公开(公告)日：2008-09-25

申请号：US11832653

申请日：2007-08-02

申请人： Wei-Zen Chen ,  Dar-Huei Liao ,  Chih-Jen Yen

发明人： Wei-Zen Chen ,  Dar-Huei Liao ,  Chih-Jen Yen

IPC分类号： H03F3/04

CPC分类号： H03F3/45475 ,  H03F1/0211 ,  H03F2200/78 ,  H03F2203/45541

摘要： A dynamic biasing amplifier apparatus, and dynamic biasing apparatus, and method are disclosed. The dynamic biasing amplifier apparatus includes a comparator unit, a dynamic bias generator unit, and an amplifier unit. The amplifier unit receives an input signal and output an output signal based on at least a bias voltage. The comparator unit compares the positive and negative input signals of the amplifier unit. The dynamic bias generator unit generates and adjusts the bias voltage in accordance with the comparing result of the comparator unit. Therefore, the dynamic bias generator unit controls the amplifier unit to operate in a low static current mode when the input signal is in steady state; and the dynamic bias generator unit controls the amplifier unit to operate in a high dynamic current mode when the input signal is in transition state.

摘要翻译： 公开了一种动态偏置放大器装置和动态偏置装置及方法。 动态偏置放大器装置包括比较器单元，动态偏置发生器单元和放大器单元。 放大器单元接收输入信号并至少基于偏置电压输出输出信号。 比较器单元比较放大器单元的正和负输入信号。 动态偏置发生器单元根据比较器单元的比较结果生成和调整偏置电压。 因此，当输入信号处于稳定状态时，动态偏置发生器单元控制放大器单元在低静态电流模式下工作; 并且当输入信号处于转换状态时，动态偏置发生器单元控制放大器单元在高动态电流模式下工作。