公开(公告)号：US08659869B2

公开(公告)日：2014-02-25

申请号：US13348761

申请日：2012-01-12

申请人： Chun I Hsieh ,  Vishwanath Bhat ,  Jennifer Sigman ,  Vassil Antonov ,  Wei Hui Hsu

发明人： Chun I Hsieh ,  Vishwanath Bhat ,  Jennifer Sigman ,  Vassil Antonov ,  Wei Hui Hsu

IPC分类号： H01G4/30

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L28/65 ,  H01L2924/0002 ,  Y10T428/265 ,  H01L2924/00

摘要： A method for forming a stacking structure, including forming a ruthenium oxide layer over a substrate; forming a praseodymium oxide layer over the ruthenium oxide layer; and forming a titanium oxide layer over the praseodymium oxide layer; wherein the titanium oxide layer has a rutile phase with the existence of the praseodymium oxide layer underneath. The oxide layers are deposited by a plurality of atomic layer deposition cycles using ruthenium precursor, praseodymium precursor, titanium precursor, and ozone.

摘要翻译： 一种用于形成堆叠结构的方法，包括在衬底上形成氧化钌层; 在氧化钌层上形成氧化镨层; 以及在所述氧化镨层上形成氧化钛层; 其中所述氧化钛层具有在其下方存在氧化镨层的金红石相。 通过使用钌前体，镨前体，钛前体和臭氧的多个原子层沉积循环来沉积氧化物层。

公开(公告)号：US08368134B2

公开(公告)日：2013-02-05

申请号：US12767639

申请日：2010-04-26

申请人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

发明人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/66583 ,  H01L21/28273 ,  H01L29/512 ,  H01L29/7887

摘要： A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的制造方法包括提供衬底。 在衬底中形成隧道绝缘层和第一导电层。 通过第一导电层和隧道绝缘层形成沟槽，其中衬底的一部分从沟槽露出。 在沟槽中形成第一绝缘层。 第二绝缘层形成在第一绝缘层的侧壁上。 第三绝缘层顺应地形成在沟槽中，覆盖沟槽底部的第一绝缘层和沟槽侧壁上的第二绝缘层，其中侧壁上的第三绝缘层的厚度比在 沟渠的底部。 控制栅极形成在沟槽中的第三绝缘层上。

公开(公告)号：US07754614B2

公开(公告)日：2010-07-13

申请号：US12016100

申请日：2008-01-17

申请人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

发明人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

IPC分类号： H01L21/311

CPC分类号： H01L29/66583 ,  H01L21/28273 ,  H01L29/512 ,  H01L29/7887

摘要： A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的制造方法包括提供衬底。 在衬底中形成隧道绝缘层和第一导电层。 通过第一导电层和隧道绝缘层形成沟槽，其中衬底的一部分从沟槽露出。 在沟槽中形成第一绝缘层。 第二绝缘层形成在第一绝缘层的侧壁上。 第三绝缘层顺应地形成在沟槽中，覆盖沟槽底部的第一绝缘层和沟槽侧壁上的第二绝缘层，其中侧壁上的第三绝缘层的厚度比在 沟渠的底部。 控制栅极形成在沟槽中的第三绝缘层上。

公开(公告)号：US20090061612A1

公开(公告)日：2009-03-05

申请号：US12016100

申请日：2008-01-17

申请人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

发明人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

IPC分类号： H01L21/3205

CPC分类号： H01L29/66583 ,  H01L21/28273 ,  H01L29/512 ,  H01L29/7887

摘要： A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的制造方法包括提供衬底。 在衬底中形成隧道绝缘层和第一导电层。 通过第一导电层和隧道绝缘层形成沟槽，其中衬底的一部分从沟槽露出。 在沟槽中形成第一绝缘层。 第二绝缘层形成在第一绝缘层的侧壁上。 第三绝缘层顺应地形成在沟槽中，覆盖沟槽底部的第一绝缘层和沟槽侧壁上的第二绝缘层，其中侧壁上的第三绝缘层的厚度比在 沟渠的底部。 控制栅极形成在沟槽中的第三绝缘层上。

公开(公告)号：US20100200903A1

公开(公告)日：2010-08-12

申请号：US12767639

申请日：2010-04-26

申请人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

发明人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

IPC分类号： H01L29/788

CPC分类号： H01L29/66583 ,  H01L21/28273 ,  H01L29/512 ,  H01L29/7887

摘要： A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的制造方法包括提供衬底。 在衬底中形成隧道绝缘层和第一导电层。 通过第一导电层和隧道绝缘层形成沟槽，其中衬底的一部分从沟槽露出。 在沟槽中形成第一绝缘层。 第二绝缘层形成在第一绝缘层的侧壁上。 第三绝缘层顺应地形成在沟槽中，覆盖沟槽底部的第一绝缘层和沟槽侧壁上的第二绝缘层，其中侧壁上的第三绝缘层的厚度比在 沟渠的底部。 控制栅极形成在沟槽中的第三绝缘层上。

公开(公告)号：US20090017604A1

公开(公告)日：2009-01-15

申请号：US11933742

申请日：2007-11-01

申请人： Mao-Ying WANG ,  Jer-Chyi WANG ,  Wei-Hui HSU ,  Liang-Pin CHOU ,  Kuo-Hui SU ,  Chang-Rong WU ,  Chao-Sung LAI

发明人： Mao-Ying WANG ,  Jer-Chyi WANG ,  Wei-Hui HSU ,  Liang-Pin CHOU ,  Kuo-Hui SU ,  Chang-Rong WU ,  Chao-Sung LAI

IPC分类号： H01L21/425

CPC分类号： H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3105 ,  H01L21/318 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate.

摘要翻译： 提供一种制造半导体器件的方法。 制造半导体器件的方法包括提供衬底。 在含有氟化氮化合物的气氛下，进行等离子体处理工艺以同时氟化和硝化基板的表面。 此后，在基板上形成电介质层。

公开(公告)号：US07696108B2

公开(公告)日：2010-04-13

申请号：US11953072

申请日：2007-12-09

申请人： Wen-Chieh Wang ,  Jin-Tau Huang ,  Wei-Hui Hsu ,  Tse-Yao Huang

发明人： Wen-Chieh Wang ,  Jin-Tau Huang ,  Wei-Hui Hsu ,  Tse-Yao Huang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/32

摘要： A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.

摘要翻译： 提供了一种在晶片斜面区域上形成阴影层的方法。 首先，提供具有晶片斜面区域和中心区域的基板。 此后，设置上绝缘体和下绝缘体。 上绝缘体设置在基板的上表面上，并且至少覆盖中心区域。 下绝缘体设置在基板的下表面上，并且至少覆盖中心区域。 然后，在未被上绝缘体覆盖的上表面上和未被下绝缘体覆盖的下表面上形成阴影层。 接下来，去除上绝缘体和下绝缘体。

公开(公告)号：US20130182367A1

公开(公告)日：2013-07-18

申请号：US13348761

申请日：2012-01-12

申请人： Chun I HSIEH ,  Vishwanath Bhat ,  Jennifer Sigman ,  Vassil Antonov ,  Wei Hui Hsu

发明人： Chun I HSIEH ,  Vishwanath Bhat ,  Jennifer Sigman ,  Vassil Antonov ,  Wei Hui Hsu

IPC分类号： H01G4/30 ,  C30B25/02 ,  B32B9/00

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L28/65 ,  H01L2924/0002 ,  Y10T428/265 ,  H01L2924/00

摘要： A method for forming a stacking structure, including forming a ruthenium oxide layer over a substrate; forming a praseodymium oxide layer over the ruthenium oxide layer; and forming a titanium oxide layer over the praseodymium oxide layer; wherein the titanium oxide layer has a rutile phase with the existence of the praseodymium oxide layer underneath. The oxide layers are deposited by a plurality of atomic layer deposition cycles using ruthenium precursor, praseodymium precursor, titanium precursor, and ozone.

摘要翻译： 一种用于形成堆叠结构的方法，包括在衬底上形成氧化钌层; 在氧化钌层上形成氧化镨层; 以及在所述氧化镨层上形成氧化钛层; 其中所述氧化钛层具有在其下方存在氧化镨层的金红石相。 通过使用钌前体，镨前体，钛前体和臭氧的多个原子层沉积循环来沉积氧化物层。

公开(公告)号：US20090023300A1

公开(公告)日：2009-01-22

申请号：US11953072

申请日：2007-12-09

申请人： Wen-Chieh Wang ,  Jin-Tau Huang ,  Wei-Hui Hsu ,  Tse-Yao Huang

发明人： Wen-Chieh Wang ,  Jin-Tau Huang ,  Wei-Hui Hsu ,  Tse-Yao Huang

IPC分类号： H01L21/469

CPC分类号： H01L21/32

摘要： A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.

摘要翻译： 提供了一种在晶片斜面区域上形成阴影层的方法。 首先，提供具有晶片斜面区域和中心区域的基板。 此后，设置上绝缘体和下绝缘体。 上绝缘体设置在基板的上表面上，并且至少覆盖中心区域。 下绝缘体设置在基板的下表面上，并且至少覆盖中心区域。 然后，在未被上绝缘体覆盖的上表面上和未被下绝缘体覆盖的下表面上形成阴影层。 接下来，去除上绝缘体和下绝缘体。