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    DRAM STACK CAPACITOR AND FABRICATION METHOD THEREOF
    1.
    发明申请
    DRAM STACK CAPACITOR AND FABRICATION METHOD THEREOF 审中-公开
    DRAM堆叠电容器及其制造方法

    公开(公告)号：US20090108319A1

    公开(公告)日：2009-04-30

    申请号：US12017164

    申请日：2008-01-21

    申请人： Teng-Wang Huang ,  Chang-Rong Wu

    发明人： Teng-Wang Huang ,  Chang-Rong Wu

    IPC分类号： H01L29/94 ,  H01L21/8242

    CPC分类号： H01L28/84 ,  H01L27/10852

    摘要： A DRAM stack capacitor and a fabrication method thereof has a first capacitor electrode formed of a conductive carbon layer overlying a semiconductor substrate, a capacitor dielectric layer and a second capacitor electrode. The first capacitor electrode is of crown shape geometry and possesses an inner surface and an outer surface. The DRAM stack capacitor features the outer surface of the first capacitor electrode as an uneven surface.

    摘要翻译： DRAM堆叠电容器及其制造方法具有由覆盖在半导体基板上的导电性碳层，电容电介质层和第二电容电极构成的第一电容电极。 第一电容器电极是冠形几何形状并具有内表面和外表面。 DRAM堆叠电容器以第一电容器电极的外表面为不平坦表面。

    Method for fabricating semiconductor device having stacked-gate structure
    2.
    发明授权
    Method for fabricating semiconductor device having stacked-gate structure 有权
    具有层叠栅结构的半导体器件的制造方法

    公开(公告)号：US07022603B2

    公开(公告)日：2006-04-04

    申请号：US10683612

    申请日：2003-10-10

    申请人： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

    发明人： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28052 ,  H01L29/4933

    摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

    摘要翻译： 一种半导体制造方法，该半导体器件具有堆叠栅极结构。 通过介电层与衬底绝缘的衬底上形成多晶硅层。 在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。 使用氮气和氢气对氮化钨层进行退火。 依次形成覆盖氮化钨层的钨层和覆盖层。

    METHOD FOR FABRICATING A BOTTLE-SHAPED DEEP TRENCH
    4.
    发明申请
    METHOD FOR FABRICATING A BOTTLE-SHAPED DEEP TRENCH 审中-公开
    用于制造瓶形深层TRENCH的方法

    公开(公告)号：US20050250345A1

    公开(公告)日：2005-11-10

    申请号：US10709444

    申请日：2004-05-06

    申请人： Chien-Jung Sun ,  Chang-Rong Wu

    发明人： Chien-Jung Sun ,  Chang-Rong Wu

    IPC分类号： H01L21/302 ,  H01L21/308 ,  H01L21/31 ,  H01L21/334 ,  H01L21/461 ,  H01L21/469 ,  H01L21/76 ,  H01L21/8242

    CPC分类号： H01L21/3083 ,  H01L27/1087 ,  H01L29/66181

    摘要： A method for fabricating a bottle-shaped deep trench. The method comprises providing a substrate having a pad layer thereon, etching the pad layer and the substrate to form a deep trench in the substrate, performing an ALD process to form a nonmetal layer on the pad layer and on an upper portion of the sidewall of the deep trench, and performing an isotropic etching process to the sidewall and the bottom surface of the deep trench by taking the nonmetal layer as a hard mask so as to form a bottle-shaped deep trench.

    摘要翻译： 一种制造瓶形深沟槽的方法。 该方法包括提供其上具有衬垫层的衬底，蚀刻衬垫层和衬底以在衬底中形成深沟槽，执行ALD工艺以在焊盘层和侧壁的上部形成非金属层 通过将非金属层作为硬掩模进行深沟槽的侧壁和底表面的各向同性蚀刻处理，以形成瓶形深沟槽。

    Method of reducing the aspect ratio of a trench
    5.
    发明授权
    Method of reducing the aspect ratio of a trench 有权
    降低沟槽纵横比的方法

    公开(公告)号：US06960530B2

    公开(公告)日：2005-11-01

    申请号：US10724435

    申请日：2003-11-28

    申请人： Chang-Rong Wu ,  Yi-Nan Chen ,  Kuo-Chien Wu ,  Hung-Chang Liao

    发明人： Chang-Rong Wu ,  Yi-Nan Chen ,  Kuo-Chien Wu ,  Hung-Chang Liao

    IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/302

    CPC分类号： H01L21/76224 ,  H01L21/31116 ,  H01L21/31612

    摘要： A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.

    摘要翻译： 减小沟槽纵横比的方法。 在衬底中形成沟槽。 通过HDPCVD在沟槽的表面上形成共形的富Si氧化物层。 通过HDPCVD在富Si氧化物层上形成保形第一氧化物层。 通过LPCVD在第一氧化物层上形成保形的第二氧化物层。 通过各向异性蚀刻去除部分富Si氧化物层，第二氧化物层和第一氧化物层，以形成由剩余的富Si氧化物层，剩余的第二氧化物层和剩余的第一氧化物层组成的氧化物间隔物。 剩余的第二氧化物层，剩余的第一氧化物层的一部分和富Si氧化物层的一部分被BOE除去。 因此，剩余的第一和富Si氧化物层的一部分形成在沟槽的下表面上，从而减小沟槽纵横比。

    Methods for manufacturing stacked gate structure and field effect transistor povided with the same
    7.
    发明申请
    Methods for manufacturing stacked gate structure and field effect transistor povided with the same 有权
    堆叠栅极结构和场效应晶体管的制造方法相同

    公开(公告)号：US20050074957A1

    公开(公告)日：2005-04-07

    申请号：US10864320

    申请日：2004-06-10

    申请人： Tzu-En Ho ,  Chang-Rong Wu

    发明人： Tzu-En Ho ,  Chang-Rong Wu

    IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/7833 ,  H01L21/28061 ,  H01L29/4933

    摘要： The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

    摘要翻译： 本发明提供一种在半导体器件中制造堆叠栅极结构的方法。 该方法包括以下步骤：在半导体衬底上依次形成栅介质层，多晶硅层，钛层和WNX层，在氮气环境中进行快速热退火（RTA），形成氮化硅 层，并且将多层薄膜结构图案化成预定的构造。

    Manufacturing method of a high aspect ratio shallow trench isolation region
    8.
    发明授权
    Manufacturing method of a high aspect ratio shallow trench isolation region 有权
    高深宽比浅沟槽隔离区的制造方法

    公开(公告)号：US06858516B2

    公开(公告)日：2005-02-22

    申请号：US10279511

    申请日：2002-10-23

    申请人： Tzu-En Ho ,  Chang Rong Wu ,  Hsin-Jung Ho

    发明人： Tzu-En Ho ,  Chang Rong Wu ,  Hsin-Jung Ho

    IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L21/76

    CPC分类号： H01L21/76224

    摘要： A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.

    摘要翻译： 高宽比浅沟槽隔离区域的制造方法。 提供其中具有沟槽的衬底并将其放置在室中。 第一绝缘层通过高密度等离子体化学气相沉积形成在衬底上以及沟内。 通过使用氟化碳作为蚀刻气体的原位蚀刻除去沟槽外部的第一绝缘层的大部分，对SiO 2 / SiN蚀刻比率具有高选择性，并且通过高密度等离子体化学品在第一绝缘层上形成第二绝缘层 气相沉积，填充沟槽。 根据本发明，可以实现无空隙的高纵横比浅沟槽隔离区域。

    1T1R resistive memory device and fabrication method thereof
    10.
    发明授权
    1T1R resistive memory device and fabrication method thereof 有权
    1T1R电阻式存储器件及其制造方法

    公开(公告)号：US08395139B1

    公开(公告)日：2013-03-12

    申请号：US13311576

    申请日：2011-12-06

    申请人： Hsin-Jung Ho ,  Chang-Rong Wu ,  Wei-Chia Chen

    发明人： Hsin-Jung Ho ,  Chang-Rong Wu ,  Wei-Chia Chen

    IPC分类号： H01L47/00

    CPC分类号： H01L27/2454 ,  H01L45/146 ,  H01L45/1683

    摘要： A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.

    摘要翻译： 存储器结构包括由第一隔离沟槽和第二隔离沟槽包围的有源区域; 凹陷到半导体衬底的有源区域中的位线沟槽; 凹入到半导体衬底的有源区域中且比位线沟槽浅的字线沟槽。 位线沟槽和字线沟槽将有源区域分成四个柱状子区域。 位线被嵌入位线沟槽中。 字线嵌入字线沟槽中。 每个柱状子区域内置有一个垂直晶体管。 电阻式存储器元件电耦合到垂直晶体管。