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1.发明授权公开(公告)号：US07230457B2
公开(公告)日：2007-06-12
申请号：US10983455
申请日：2004-11-08
申请人： William C. Waldrop
发明人： William C. Waldrop
IPC分类号： H03K3/00
CPC分类号： H04L25/028 , H03K19/00315 , H03K19/018585 , H04L25/085
摘要： An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.
摘要翻译： 讨论了包括具有用于驱动数据总线的两种操作模式的数据输出驱动器的集成电路器件。 输出驱动器包括产生全驱动输出高信号，部分驱动输出高信号，全驱动输出低信号和部分驱动输出低信号的电路。 输出驱动器可以防止数据总线上的负电压。 输出驱动器是可选择的，适用于驱动端接负载和未终端负载。
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公开(公告)号：US06549041B2
公开(公告)日：2003-04-15
申请号：US10208063
申请日：2002-07-30
申请人： William C. Waldrop
发明人： William C. Waldrop
IPC分类号： G01R2500
CPC分类号： H03L7/0814 , H03L7/095 , H03L7/10 , H03L7/107 , H03L2207/14
摘要： Systems and methods are provided for operating a delay locked loop during a reset. The systems and methods provide for activating a reset mode signal to prevent a phase lock signal from forcing the DLL out of a reset, and deactivating the reset mode signal only after at least one shifting operation is performed to allow the phase lock signal to correctly allow the DLL to be out of the reset.
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公开(公告)号：US06452431B1
公开(公告)日：2002-09-17
申请号：US09649691
申请日：2000-08-28
申请人： William C. Waldrop
发明人： William C. Waldrop
IPC分类号： H03L706
CPC分类号： H03L7/0814 , H03L7/095 , H03L7/10 , H03L7/107 , H03L2207/14
摘要： Systems and methods are provided for operating a delay locked loop during a reset. The systems and methods provide for activating a reset mode signal to prevent a phase lock signal from forcing the DLL out of a reset, and deactivating the reset mode signal only after at least one shifting operation is performed to allow the phase lock signal to correctly allow the DLL to be out of the reset.
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公开(公告)号：US09479361B2
公开(公告)日：2016-10-25
申请号：US13071287
申请日：2011-03-24
申请人： William C. Waldrop
发明人： William C. Waldrop
IPC分类号： H03K19/00 , H04L25/02 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4096
CPC分类号： H04L25/0278 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
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5.发明申请公开(公告)号：US20110169529A1
公开(公告)日：2011-07-14
申请号：US13071287
申请日：2011-03-24
申请人： William C. Waldrop
发明人： William C. Waldrop
IPC分类号： H03K5/19
CPC分类号： H04L25/0278 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译： 操作诸如存储器芯片的电子设备的系统和方法具有被配置为包括ODT（片上终端）模式检测器的输出驱动器电路，检测是否存在足够的可用于操作ODT部分的内部时钟 输出驱动器处于同步操作模式或将操作切换到异步模式。 基于时钟的内部ODT操作模式（同步与异步）的确定避免了输出驱动器中ODT控制单元中复杂且不灵活的时钟处理逻辑的使用。 这使得能够在各种设备操作模式（例如，有功，掉电等）期间对ODT电路的实际时钟进行改变，而不需要为这些模式中的每一个重新设计ODT控制逻辑。 ODT模式检测器设计的简单性和灵活性允许有效地利用芯片的不动产而不影响电子设备中输出驱动器的信号传输速度。 由于管理摘要的规则，本摘要不应用于解释索赔。
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公开(公告)号：US06975149B2
公开(公告)日：2005-12-13
申请号：US10944136
申请日：2004-09-16
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , H03L7/0812
摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
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7.发明授权公开(公告)号：US06885226B2
公开(公告)日：2005-04-26
申请号：US10431161
申请日：2003-05-06
申请人： William C. Waldrop
发明人： William C. Waldrop
IPC分类号： H03K19/003 , H03K19/0185 , H03K3/00
CPC分类号： H04L25/028 , H03K19/00315 , H03K19/018585 , H04L25/085
摘要： An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.
摘要翻译： 讨论了包括具有用于驱动数据总线的两种操作模式的数据输出驱动器的集成电路器件。 输出驱动器包括产生全驱动输出高信号，部分驱动输出高信号，全驱动输出低信号和部分驱动输出低信号的电路。 输出驱动器可以防止数据总线上的负电压。 输出驱动器是可选择的，适用于驱动端接负载和未终端负载。
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公开(公告)号：US06329867B1
公开(公告)日：2001-12-11
申请号：US09390741
申请日：1999-09-07
IPC分类号： H03K1728
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C11/4093 , H03K5/1534
摘要： A circuit is designed with a delay circuit (300) coupled to receive a clock input signal (CLK) and a control signal (DFT). The control signal has a first logic state and a second logic state. The delay circuit produces a clock control signal (*CLK) at a first time in response to the first logic state and at a second time in response to the second logic state. A clock circuit (200) is coupled to receive the clock input signal and is enabled by the clock control signal. The clock circuit produces a first clock pulse signal having a predetermined width in response to a first transition of the clock input signal and produces a second clock pulse signal having the predetermined width in response to a second transition of the clock input signal.
摘要翻译： 电路被设计成具有连接以接收时钟输入信号（CLK）和控制信号（DFT）的延迟电路（300）。 控制信号具有第一逻辑状态和第二逻辑状态。 延迟电路响应于第一逻辑状态在第一时间产生时钟控制信号（* CLK），并响应于第二逻辑状态在第二时间产生时钟控制信号（* CLK）。 时钟电路（200）被耦合以接收时钟输入信号，并且由时钟控制信号使能。 响应于时钟输入信号的第一次转换，时钟电路产生具有预定宽度的第一时钟脉冲信号，并响应于时钟输入信号的第二转换产生具有预定宽度的第二时钟脉冲信号。
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公开(公告)号：US06819151B2
公开(公告)日：2004-11-16
申请号：US10651602
申请日：2003-08-29
IPC分类号： H03L700
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , H03L7/0812
摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
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10.发明授权公开(公告)号：US06605969B2
公开(公告)日：2003-08-12
申请号：US09974322
申请日：2001-10-09
IPC分类号： H03L706
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , H03L7/0812
摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
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