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公开(公告)号：US09083322B2
公开(公告)日：2015-07-14
申请号：US13180801
申请日：2011-07-12
申请人： William D. Llewellyn
发明人： William D. Llewellyn
CPC分类号： H03K4/023
摘要： An apparatus includes a capacitor, a current generating circuit communicatively coupled to the capacitor, and a current pulse timing circuit communicatively coupled to the current source circuit. The current timing pulse circuit is configured to time durations of a first plurality of current pulses from the current generating circuit for charging the capacitor and a second plurality of current pulses for discharging the capacitor, and step the durations of the current pulses between a minimum duty cycle and a maximum duty cycle. A cycle of providing the first plurality of current pulses and providing the second plurality of current pulses results in generation of a subsonic pseudo-sinusoidal pulse signal at the capacitor.
摘要翻译： 一种装置包括电容器，通信地耦合到电容器的电流产生电路，以及通信地耦合到电流源电路的电流脉冲定时电路。 当前定时脉冲电路被配置为从用于对电容器充电的电流产生电路的第一多个电流脉冲的持续时间和用于放电电容器的第二多个电流脉冲持续时间，并且将电流脉冲的持续时间在最小负载 周期和最大占空比。 提供第一多个电流脉冲并提供第二多个电流脉冲的循环导致在电容器处产生亚音速伪正弦脉冲信号。
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公开(公告)号：US08866544B2
公开(公告)日：2014-10-21
申请号：US13445574
申请日：2012-04-12
申请人： William D. Llewellyn
发明人： William D. Llewellyn
摘要： This document discusses, among other things, a modulator including a first integrator configured to receive an input signal and a first feedback signal from an output stage, a second integrator configured to receive an output of the first integrator and a second feedback signal, and a comparator configured to be coupled to a regulated supply voltage, to receive an output of the second integrator and a modulation signal, and to provide a pulse width modulated representation of the input signal. The output stage is configured to be coupled to an unregulated supply voltage, and the second feedback signal can include a representation of an output of the comparator configured to reduce artifacts in the pulse width modulated representation of the input signal induced by changes in an amplitude of the unregulated supply voltage.
摘要翻译： 该文件尤其涉及包括配置成从输出级接收输入信号和第一反馈信号的第一积分器的调制器，被配置为接收第一积分器的输出和第二反馈信号的第二积分器，以及 比较器被配置为耦合到稳压电源电压，以接收第二积分器的输出和调制信号，并提供输入信号的脉宽调制表示。 输出级被配置为耦合到未调节的电源电压，并且第二反馈信号可以包括比较器的输出的表示，所述比较器的输出被配置为减少由于振幅的变化引起的输入信号的脉宽调制表示中的伪像 电源电压不稳定。
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公开(公告)号：US20130016844A1
公开(公告)日：2013-01-17
申请号：US13180801
申请日：2011-07-12
申请人： William D. Llewellyn
发明人： William D. Llewellyn
CPC分类号： H03K4/023
摘要： An apparatus includes a capacitor, a current generating circuit communicatively coupled to the capacitor, and a current pulse timing circuit communicatively coupled to the current source circuit. The current timing pulse circuit is configured to time durations of a first plurality of current pulses from the current generating circuit for charging the capacitor and a second plurality of current pulses for discharging the capacitor, and step the durations of the current pulses between a minimum duty cycle and a maximum duty cycle. A cycle of providing the first plurality of current pulses and providing the second plurality of current pulses results in generation of a subsonic pseudo-sinusoidal pulse signal at the capacitor.
摘要翻译： 一种装置包括电容器，通信地耦合到电容器的电流产生电路，以及通信地耦合到电流源电路的电流脉冲定时电路。 当前定时脉冲电路被配置为从用于对电容器充电的电流产生电路的第一多个电流脉冲的持续时间和用于放电电容器的第二多个电流脉冲持续时间，并且将电流脉冲的持续时间在最小负载 周期和最大占空比。 提供第一多个电流脉冲并提供第二多个电流脉冲的循环导致在电容器处产生亚音速伪正弦脉冲信号。
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公开(公告)号：US5912779A
公开(公告)日：1999-06-15
申请号：US758794
申请日：1996-12-02
IPC分类号： G11B5/012 , G11B5/02 , G11B5/09 , G11B5/127 , G11B5/29 , G11B5/31 , G11B5/48 , G11B11/105 , G11B20/10 , G11B20/14 , G11B20/20 , G11B23/00
CPC分类号： G11B20/10222 , G11B11/10534 , G11B11/10552 , G11B20/10009 , G11B20/1403 , G11B20/20 , G11B5/012 , G11B5/02 , G11B5/09 , G11B5/127 , G11B5/29 , G11B5/31 , G11B5/313 , G11B5/488 , G11B5/4886 , G11B23/0007
摘要： A multiple-gap head for transferring data to or from a storage medium is disclosed. Data read by the gaps are directed over a plurality of serial data paths where the data are processed and synchronized. In some embodiments, all or part of a data synchronizer is shared by the serial data paths. The data are then assembled into a parallel data stream for delivery to a computer. Reading the data simultaneously with multiple gaps increases by several times the rate at which data can be transferred to or from a storage medium. In accordance with another aspect of the invention, a three-gap head is provided to reduce or eliminate the cross-talk or noise fringe problems which reduce the track density in a storage medium. A signal attenuator and a signal inverter are connected to each of the side gaps and the outputs thereof are summed with the signal originating at the center gap, such that the inverted signals from the side gaps cancel any cross-talk originating at the center gap. Similarly, an attenuator and an inverter are connected between the write data path (leading to the center gap) and each of the side gaps. During write operations the magnetic flux produced at each of the side gaps has the effect of focusing the magnetic flux produced at the center gap, thereby reducing or eliminating the noise fringe of the written data track.
摘要翻译： 公开了用于向存储介质传送数据或从存储介质传送数据的多间隙头。 由间隙读取的数据被引导到数据被处理和同步的多个串行数据路径上。 在一些实施例中，数据同步器的全部或部分由串行数据路径共享。 然后将数据组装成并行数据流以传送到计算机。 以多个间隙同时读取数据可以将数据传输到存储介质或从存储介质传输的速率增加几倍。 根据本发明的另一方面，提供三间隙头以减少或消除减少存储介质中的轨道密度的串扰或噪声边缘问题。 信号衰减器和信号反相器连接到每个侧面间隙，并且其输出与起始于中心间隙的信号相加，使得来自侧面间隙的反相信号抵消在中心间隙处产生的任何串扰。 类似地，衰减器和反相器连接在写入数据路径（通向中心间隙）和每个侧面间隙之间。 在写入操作期间，在每个侧面间隙处产生的磁通具有聚焦在中心间隙处产生的磁通量的作用，从而减少或消除了写入数据轨迹的噪声边缘。
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公开(公告)号：US5426539A
公开(公告)日：1995-06-20
申请号：US984660
申请日：1992-12-01
IPC分类号： G11B5/012 , G11B5/02 , G11B5/09 , G11B5/127 , G11B5/29 , G11B5/31 , G11B5/48 , G11B11/105 , G11B20/10 , G11B20/14 , G11B20/20 , G11B23/00
CPC分类号： G11B20/10222 , G11B11/10534 , G11B11/10552 , G11B20/10009 , G11B20/1403 , G11B20/20 , G11B5/012 , G11B5/02 , G11B5/09 , G11B5/127 , G11B5/29 , G11B5/31 , G11B5/313 , G11B5/488 , G11B5/4886 , G11B23/0007
摘要： A multiple-gap head for transferring data to or from a storage medium is disclosed. Data read by the gaps are directed over a plurality of serial data paths where the data are processed and synchronized. In some embodiments, all or part of a data synchronizer is shared by the serial data paths. The data are then assembled into a parallel data stream for delivery to a computer. Reading the data simultaneously with multiple gaps increases by several times the rate at which data can be transferred to or from a storage medium. In accordance with another aspect of the invention, a three-gap head is provided to reduce or eliminate the cross-talk or noise fringe problems which reduce the track density in a storage medium. A signal attenuator and a signal inverter are connected to each of the side gaps and the outputs thereof are summed with the signal originating at the center gap, such that the inverted signals from the side gaps cancel any cross-talk originating at the center gap. Similarly, an attenuator and an inverter are connected between the write data path (leading to the center gap) and each of the side gaps. During write operations the magnetic flux produced at each of the side gaps has the effect of focusing the magnetic flux produced at the center gap, thereby reducing or eliminating the noise fringe of the written data track.
摘要翻译： 公开了用于向存储介质传送数据或从存储介质传送数据的多间隙头。 由间隙读取的数据被引导到数据被处理和同步的多个串行数据路径上。 在一些实施例中，数据同步器的全部或部分由串行数据路径共享。 然后将数据组装成并行数据流以传送到计算机。 以多个间隙同时读取数据可以将数据传输到存储介质或从存储介质传输的速率增加几倍。 根据本发明的另一方面，提供三间隙头以减少或消除减少存储介质中的轨道密度的串扰或噪声边缘问题。 信号衰减器和信号反相器连接到每个侧面间隙，并且其输出与起始于中心间隙的信号相加，使得来自侧面间隙的反相信号抵消在中心间隙处产生的任何串扰。 类似地，衰减器和反相器连接在写入数据路径（通向中心间隙）和每个侧面间隙之间。 在写入操作期间，在每个侧面间隙处产生的磁通具有聚焦在中心间隙处产生的磁通量的作用，从而减少或消除了写入数据轨迹的噪声边缘。
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公开(公告)号：US08831230B2
公开(公告)日：2014-09-09
申请号：US13272021
申请日：2011-10-12
CPC分类号： H03F3/45475 , H03F3/187 , H03F3/68 , H03F2203/45522 , H03F2203/45591 , H04R5/04
摘要： This document discusses apparatus and methods for configuring and providing crosstalk cancellation to maintain channel separation in a multi channel system. In an example, an amplifier circuit can include a crosstalk cancellation circuit configured to reduce crosstalk from a first output to a second load and from a second output to a first load where the first load and the second load share a return path.
摘要翻译： 本文讨论了用于配置和提供串扰消除以维持多信道系统中的信道分离的装置和方法。 在一个示例中，放大器电路可以包括串扰消除电路，其被配置为减少从第一输出到第二负载的串扰，以及从第二输出到第一负载的第一负载，其中第一负载和第二负载共享返回路径。
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公开(公告)号：US08638148B2
公开(公告)日：2014-01-28
申请号：US12899810
申请日：2010-10-07
申请人： William D. Llewellyn
发明人： William D. Llewellyn
IPC分类号： H03K5/12
CPC分类号： H03K17/164
摘要： This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal.
摘要翻译： 本文件尤其讨论了用于减少开关信号的电磁干扰的系统和方法。 在一个示例中，可以在输入处接收切换的输入信号，并且可以响应于所接收的切换输入信号来控制边沿速率控制的切换输出信号的转变速率。
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公开(公告)号：US20100001799A1
公开(公告)日：2010-01-07
申请号：US12425790
申请日：2009-04-17
申请人： William D. Llewellyn
发明人： William D. Llewellyn
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/0227 , H03F3/3069 , H03F2200/03 , H03F2200/33 , H03F2200/453 , H03F2200/511 , H03F2203/45138
摘要： A drive current direction between first and second amplifiers can be selected using a received indication of an output current in an at least partially reactive load, and an amplified output signal can be produced using the selected drive current direction and the first and second amplifiers. Further, the first and second amplifiers can be configured to alternate between a pull-up mode and a pull-down mode, each amplifying half of a full wave output signal.
摘要翻译： 可以使用在至少部分无功负载中的输出电流的接收指示来选择第一和第二放大器之间的驱动电流方向，并且可以使用所选择的驱动电流方向和第一和第二放大器来产生放大的输出信号。 此外，第一和第二放大器可以被配置为在上拉模式和下拉模式之间交替，每一个放大全波输出信号的一半。
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公开(公告)号：US07026866B2
公开(公告)日：2006-04-11
申请号：US10807903
申请日：2004-03-23
申请人： William D. Llewellyn
发明人： William D. Llewellyn
IPC分类号： H03F1/02
CPC分类号： H03F3/2173
摘要： Techniques for DC offset cancellation are described. According to one embodiment, an amplifier has at least one output and first and second supply rails. The amplifier includes offset cancellation logic which is operable in a calibration mode to generate a first offset cancellation signal when the at least one output is coupled to a first voltage corresponding to the first supply rail, and a second offset cancellation signal when the at least one output is coupled to a second voltage corresponding to the second supply rail. The offset cancellation logic is further operable to facilitate at least partial cancellation of an offset voltage associated with the at least one output during a normal operation mode using a third offset cancellation signal which substantially corresponds to an average of the first and second offset cancellation signals.
摘要翻译： 描述了用于DC偏移消除的技术。 根据一个实施例，放大器具有至少一个输出和第一和第二电源轨。 所述放大器包括偏移消除逻辑，当所述至少一个输出耦合到对应于所述第一电源轨的第一电压时，所述偏移消除逻辑可在校准模式下操作以产生第一偏移消除信号，以及当所述至少一个 输出耦合到对应于第二电源轨的第二电压。 偏移消除逻辑还可操作以便在正常操作模式期间使用基本对应于第一和第二偏移消除信号的平均值的第三偏移消除信号来促进与至少一个输出相关联的偏移电压的至少部分消除。
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公开(公告)号：US06566946B2
公开(公告)日：2003-05-20
申请号：US09908862
申请日：2001-07-18
申请人： William D. Llewellyn
发明人： William D. Llewellyn
IPC分类号： H03F345
CPC分类号： H03F1/26 , H03F3/45475 , H03F3/45479 , H03F2203/45528
摘要： Methods and apparatus are described for generating or amplifying a differential signal. The output of a first op amp corresponds to one end of the differential signal. The output of a second op amp corresponds to the other end of the differential signal. The inverting input of the first op amp is coupled to the noninverting input of the second op amp.
摘要翻译： 描述了用于产生或放大差分信号的方法和装置。 第一运算放大器的输出对应于差分信号的一端。 第二运算放大器的输出对应于差分信号的另一端。 第一运算放大器的反相输入耦合到第二运算放大器的同相输入。
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