公开(公告)号：US20110127070A1

公开(公告)日：2011-06-02

申请号：US12956545

申请日：2010-11-30

申请人： Chi Hee Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Jin Su Kim ,  Sung Woon Yoon ,  Myoung Hwa Nam

发明人： Chi Hee Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Jin Su Kim ,  Sung Woon Yoon ,  Myoung Hwa Nam

IPC分类号： H05K1/02 ,  B32B37/22 ,  H05K3/00

CPC分类号： H05K3/465 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/107 ,  H05K3/184 ,  H05K3/4661 ,  H05K2203/054 ,  Y10T29/49124 ,  Y10T29/49155

摘要： An embedded PCB, a multi-layer PCB using the embedded PCB, and a method of manufacturing the same are provided. The method of manufacturing an embedded PCB includes a first step of patterning an insulating layer on which a photoresist layer is formed using a laser such that parts of the insulating layer are selectively etched to form a circuit pattern region and a second step of filling the circuit pattern region with a plating material to form a circuit pattern. Accordingly, the method of manufacturing an embedded PCB can simultaneously or sequentially etch a photoresist layer and an insulating layer using a laser to form a circuit pattern so as to obtain a micro pattern and simplify a manufacturing process and achieve alignment accuracy in construction of a multi-layer PCB using the embedded PCB to thereby improve product reliability and yield.

摘要翻译： 提供嵌入式PCB，使用嵌入式PCB的多层PCB及其制造方法。 制造嵌入式PCB的方法包括：使用激光使绝缘层图案化的第一步骤，使得绝缘层的一部分被选择性地蚀刻以形成电路图案区域;以及第二步骤， 图案区域与电镀材料形成电路图案。 因此，制造嵌入式PCB的方法可以使用激光器同时或顺序地蚀刻光致抗蚀剂层和绝缘层，以形成电路图案，从而获得微图案并简化制造工艺，并实现多层结构的对准精度 使用嵌入式PCB的PCB层，从而提高产品的可靠性和产量。

公开(公告)号：US09532462B2

公开(公告)日：2016-12-27

申请号：US13512271

申请日：2010-11-25

申请人： Yeong Uk Seo ,  Sung Woon Yoon ,  Jin Su Kim ,  Myoung Hwa Nam ,  Sang Myung Lee ,  Chi Hee Ahn

发明人： Yeong Uk Seo ,  Sung Woon Yoon ,  Jin Su Kim ,  Myoung Hwa Nam ,  Sang Myung Lee ,  Chi Hee Ahn

IPC分类号： H05K1/00 ,  H05K1/09 ,  H05K3/10 ,  H05K3/20 ,  H05K1/02 ,  H05K1/03 ,  H05K3/02

CPC分类号： H05K3/101 ,  H05K1/02 ,  H05K1/0353 ,  H05K1/092 ,  H05K3/02 ,  H05K3/108 ,  H05K3/20 ,  H05K2201/0376 ,  H05K2203/0278

摘要： The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.

摘要翻译： 本发明提供一种印刷电路板的结构及其制造方法。 该方法包括：（a）在形成种子层的绝缘层上形成电路图形; （b）通过压制方法将电路图案嵌入绝缘层; 和（c）去除种子层。 根据本发明，可以通过在绝缘层上直接形成电路图案而形成不发生取向问题的精细图案，并且通过执行将突出电路嵌入绝缘层中的工艺可以提高形成的精细图案的可靠性。 此外，通过在去除种子层的蚀刻工艺期间，通过在电路层上过度蚀刻比低于绝缘层的表面的电路层，由于相邻电路之间的离子迁移而发生劣质电路的可能性可能会降低。

公开(公告)号：US20130112463A1

公开(公告)日：2013-05-09

申请号：US13512271

申请日：2010-11-25

申请人： Yeong Uk Seo ,  Sung Woon Yoon ,  Jin Su Kim ,  Myoung Hwa Nam ,  Sang Myung Lee ,  Chi Hee Ahn

发明人： Yeong Uk Seo ,  Sung Woon Yoon ,  Jin Su Kim ,  Myoung Hwa Nam ,  Sang Myung Lee ,  Chi Hee Ahn

IPC分类号： H05K3/10 ,  H05K1/09 ,  H05K1/03 ,  H05K1/02

CPC分类号： H05K3/101 ,  H05K1/02 ,  H05K1/0353 ,  H05K1/092 ,  H05K3/02 ,  H05K3/108 ,  H05K3/20 ,  H05K2201/0376 ,  H05K2203/0278

摘要： The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.

摘要翻译： 本发明提供一种印刷电路板的结构及其制造方法。 该方法包括：（a）在形成种子层的绝缘层上形成电路图形; （b）通过压制方法将电路图案嵌入绝缘层; 和（c）去除种子层。 根据本发明，可以通过在绝缘层上直接形成电路图案而形成不发生取向问题的精细图案，并且通过执行将突出电路嵌入绝缘层中的工艺可以提高形成的精细图案的可靠性。 此外，通过在去除种子层的蚀刻工艺期间，通过在电路层上过度蚀刻比低于绝缘层的表面的电路层，由于相邻电路之间的离子迁移而发生劣质电路的可能性可能会降低。

公开(公告)号：US20130062106A1

公开(公告)日：2013-03-14

申请号：US13512748

申请日：2010-11-26

申请人： Jin Su Kim ,  Duk Nam Kim ,  Jae Hyun Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Chi Hee Ahn ,  Sung Woon Yoon ,  Myoung Hwa Nam

发明人： Jin Su Kim ,  Duk Nam Kim ,  Jae Hyun Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Chi Hee Ahn ,  Sung Woon Yoon ,  Myoung Hwa Nam

IPC分类号： H05K3/10 ,  H05K1/09 ,  H05K1/11

CPC分类号： H05K3/4658 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4647 ,  H05K2203/0108 ,  Y10T29/49155

摘要： A structure of a printed circuit board and a method of manufacturing the same are provided. The manufacturing method includes a first step of forming at least one connecting bump on first circuit patterns and forming a first insulating layer to form an inner circuit board, a second step of processing a second insulating layer with a metal seed layer formed thereon using a mold to form second circuit patterns so as to construct an outer circuit board, and a third step of aligning the inner circuit board and the outer circuit board with each other and laminating the inner circuit board and the outer circuit board. Accordingly, a structure of a high-density high-reliability printed circuit board having a circuit embedded in an insulating layer can be provided. A seed layer forming process for forming an outmost circuit can be removed by using an insulating layer combined with a seed layer. In addition, a conductive structure in the form of a connecting bump is formed, and thus a complicated process of forming a via-hole and filling the via-hole with a conductive material is not required. Furthermore, a process of grinding the surface of the filled conductive material is removed so as to remarkably decrease a circuit error rate.

摘要翻译： 提供一种印刷电路板的结构及其制造方法。 该制造方法包括：在第一电路图案上形成至少一个连接凸块并形成第一绝缘层以形成内部电路板的第一步骤;使用模具处理其上形成有金属晶种层的第二绝缘层的第二步骤 以形成第二电路图案以构成外部电路板，以及将内部电路板和外部电路板彼此对准并层压内部电路板和外部电路板的第三步骤。 因此，可以提供具有嵌入在绝缘层中的电路的高密度高可靠性印刷电路板的结构。 可以通过使用与种子层结合的绝缘层来去除用于形成最外层电路的籽晶层形成工艺。 此外，形成连接凸块形式的导电结构，因此不需要形成通孔并且用导电材料填充通孔的复杂工艺。 此外，去除了填充的导电材料的表面的研磨过程，以显着降低电路错误率。

公开(公告)号：US09491866B2

公开(公告)日：2016-11-08

申请号：US13809083

申请日：2011-07-07

申请人： Sang Myung Lee ,  Byeong Ho Kim ,  Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Sung Woon Yoon

发明人： Sang Myung Lee ,  Byeong Ho Kim ,  Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Sung Woon Yoon

IPC分类号： H05K3/06 ,  H05K3/10 ,  H05K3/00 ,  H05K3/02 ,  H05K3/46 ,  H05K3/04

CPC分类号： H05K3/062 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/02 ,  H05K3/045 ,  H05K3/108 ,  H05K3/465 ,  H05K2203/0554 ,  H05K2203/0557 ,  Y10T29/49167

摘要： Provided is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes preparing an insulation board, irradiating a laser onto a graytone mask to each a surface of the insulation board, thereby forming a circuit pattern groove and a via hole at the same time, and filling the circuit pattern groove and the via hole to form a buried circuit pattern and the via. Thus, the circuit pattern groove and the via hole may be formed using the graytone mask at the same time without perfolining a separate process for forming the via hole. Therefore, the manufacturing process may be simplified to reduce the manufacturing costs.

摘要翻译： 提供一种印刷电路板的制造方法。 制造印刷电路板的方法包括制备绝缘板，将激光照射到灰蒙蒙掩模到绝缘板的每个表面上，从而同时形成电路图案槽和通孔，并填充电路图案 沟槽和通孔形成掩埋电路图案和通孔。 因此，电路图案槽和通孔可以同时使用灰蒙版掩模形成，而不需要单独的用于形成通孔的工艺。 因此，可以简化制造过程以降低制造成本。

公开(公告)号：US09265161B2

公开(公告)日：2016-02-16

申请号：US12956545

申请日：2010-11-30

申请人： Chi Hee Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Jin Su Kim ,  Sung Woon Yoon ,  Myoung Hwa Nam

发明人： Chi Hee Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Jin Su Kim ,  Sung Woon Yoon ,  Myoung Hwa Nam

IPC分类号： H05K3/02 ,  H05K3/10 ,  H05K3/46 ,  H05K3/18 ,  H05K3/00 ,  H05K3/04

CPC分类号： H05K3/465 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/107 ,  H05K3/184 ,  H05K3/4661 ,  H05K2203/054 ,  Y10T29/49124 ,  Y10T29/49155

摘要： An embedded PCB, a multi-layer PCB using the embedded PCB, and a method of manufacturing the same are provided. The method of manufacturing an embedded PCB includes a first step of patterning an insulating layer on which a photoresist layer is formed using a laser such that parts of the insulating layer are selectively etched to form a circuit pattern region and a second step of filling the circuit pattern region with a plating material to form a circuit pattern. Accordingly, the method of manufacturing an embedded PCB can simultaneously or sequentially etch a photoresist layer and an insulating layer using a laser to form a circuit pattern so as to obtain a micro pattern and simplify a manufacturing process and achieve alignment accuracy in construction of a multi-layer PCB using the embedded PCB to thereby improve product reliability and yield.

摘要翻译： 提供嵌入式PCB，使用嵌入式PCB的多层PCB及其制造方法。 制造嵌入式PCB的方法包括：使用激光使绝缘层图案化的第一步骤，使得绝缘层的一部分被选择性地蚀刻以形成电路图案区域;以及第二步骤， 图案区域与电镀材料形成电路图案。 因此，制造嵌入式PCB的方法可以使用激光器同时或顺序地蚀刻光致抗蚀剂层和绝缘层，以形成电路图案，从而获得微图案并简化制造工艺，并实现多层结构的对准精度 使用嵌入式PCB的PCB层，从而提高产品的可靠性和产量。

公开(公告)号：US08659131B2

公开(公告)日：2014-02-25

申请号：US13121018

申请日：2009-09-25

申请人： Ji Yun Kim ,  Hyun Sub Shin ,  Sung Won Lee ,  Hyung Eui Lee ,  Yeong Uk Seo ,  Sung Wuk Ryu ,  Hyuk Soo Lee

发明人： Ji Yun Kim ,  Hyun Sub Shin ,  Sung Won Lee ,  Hyung Eui Lee ,  Yeong Uk Seo ,  Sung Wuk Ryu ,  Hyuk Soo Lee

IPC分类号： H01L23/495

CPC分类号： H01L21/4832 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/95 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85457 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.

摘要翻译： 本发明涉及多排引线框架和半导体封装的结构和制造方法，其特征在于在金属材料上形成焊盘部分（第一步骤）; 在第一图案形成之后执行表面电镀工艺或有机材料涂层（第二步骤）; 在金属材料上形成第二图案（第三步骤）; 并且在第二图案形成之后封装半导体芯片（第四步骤），由此通过施加渐进蚀刻来最小化底切现象。

公开(公告)号：US20120255764A1

公开(公告)日：2012-10-11

申请号：US13500754

申请日：2010-08-05

申请人： Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Chi Hee Ahn

发明人： Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Chi Hee Ahn

IPC分类号： H05K3/00 ,  G03F7/20 ,  H05K1/02

CPC分类号： H05K3/205 ,  H05K3/107 ,  H05K3/108 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/0355 ,  H05K2203/0108 ,  Y10T156/10

摘要： An embedded printed circuit board and a manufacturing method thereof are provided. The manufacturing method includes a first step of forming a first insulating layer having a seed layer formed on one side thereof and at least. one metal pattern embedded therein and a second step of laminating the first insulating layer and a base substrate with an inner circuit having a second insulating layer interposed between the first insulating layer and the base substrate. Accordingly, a printed circuit board with a circuit embedded in an insulating layer is provided, and thus a high-density and high-reliability printed circuit board can be achieved. Furthermore, since the printed circuit board is manufactured using a mold, a circuit manufacturing process for embedding, a process for forming a seed layer and a complicated process such as surface grinding are omitted so as to simplify the manufacturing process.

摘要翻译： 提供一种嵌入式印刷电路板及其制造方法。 该制造方法包括：形成第一绝缘层的第一工序，该第一绝缘层的至少一面形成有种子层。 嵌入其中的一个金属图案，以及第二步骤，用第一绝缘层和基底衬底之间的具有第二绝缘层的内部电路层叠第一绝缘层和基底。 因此，提供了具有嵌入在绝缘层中的电路的印刷电路板，因此可以实现高密度和高可靠性的印刷电路板。 此外，由于使用模具制造印刷电路板，所以省略了用于嵌入的电路制造工艺，用于形成种子层的工艺和诸如表面磨削的复杂工艺，以简化制造工艺。

公开(公告)号：US20130192881A1

公开(公告)日：2013-08-01

申请号：US13809083

申请日：2011-07-07

申请人： Sang Myung Lee ,  Byeong Ho Kim ,  Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Sung Woon Yoon

发明人： Sang Myung Lee ,  Byeong Ho Kim ,  Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Sung Woon Yoon

IPC分类号： H05K1/02

CPC分类号： H05K3/062 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/02 ,  H05K3/045 ,  H05K3/108 ,  H05K3/465 ,  H05K2203/0554 ,  H05K2203/0557 ,  Y10T29/49167

摘要： Provided is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes preparing an insulation board, irradiating a laser onto a graytone mask to each a surface of the insulation board, thereby forming a circuit pattern groove and a via hole at the same time, and filling the circuit pattern groove and the via hole to form a buried circuit pattern and the via. Thus, the circuit pattern groove and the via hole may be formed using the graytone mask at the same time without performing a separate process for forming the via hole. Therefore, the manufacturing process may be simplified to reduce the manufacturing costs.

摘要翻译： 提供一种印刷电路板的制造方法。 制造印刷电路板的方法包括制备绝缘板，将激光照射到灰蒙蒙掩模到绝缘板的每个表面上，从而同时形成电路图案槽和通孔，并填充电路图案 沟槽和通孔形成掩埋电路图案和通孔。 因此，电路图案槽和通孔可以使用灰蒙版掩模同时形成，而不进行用于形成通孔的单独处理。 因此，可以简化制造过程以降低制造成本。

公开(公告)号：US20110227208A1

公开(公告)日：2011-09-22

申请号：US13121018

申请日：2009-09-25

申请人： Ji Yun Kim ,  Hyun Sub Shin ,  Sung Won Lee ,  Hyung Eui Lee ,  Yeong Uk Seo ,  Sung Wuk Ryu ,  Hyuk Soo Lee

发明人： Ji Yun Kim ,  Hyun Sub Shin ,  Sung Won Lee ,  Hyung Eui Lee ,  Yeong Uk Seo ,  Sung Wuk Ryu ,  Hyuk Soo Lee

IPC分类号： H01L23/495 ,  H01L21/64 ,  H05K3/00 ,  G03F7/20

CPC分类号： H01L21/4832 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/95 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85457 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.

摘要翻译： 本发明涉及多排引线框架和半导体封装的结构和制造方法，其特征在于在金属材料上形成焊盘部分（第一步骤）; 在第一图案形成之后执行表面电镀工艺或有机材料涂层（第二步骤）; 在金属材料上形成第二图案（第三步骤）; 并且在第二图案形成之后封装半导体芯片（第四步骤），由此通过施加渐进蚀刻来最小化底切现象。