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    SPLIT GATE FLASH CELL AND METHOD FOR MAKING THE SAME
    1.
    发明申请
    SPLIT GATE FLASH CELL AND METHOD FOR MAKING THE SAME 有权
    分离栅格闪存单元及其制造方法

    公开(公告)号：US20140027833A1

    公开(公告)日：2014-01-30

    申请号：US14038410

    申请日：2013-09-26

    申请人： Yimin WANG

    发明人： Yimin WANG

    IPC分类号： H01L27/088

    CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/088 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324

    摘要： A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.

    摘要翻译： 提供了具有浮动栅极晶体管的分离栅极闪存单元器件。 每个浮栅晶体管通过提供浮置晶体管子结构形成，该浮动栅极晶体管子结构包括设置在设置在公共源的一部分上的栅极氧化物上的多晶硅栅极上的氧化物。 氮化物间隔物沿着浮栅晶体管子结构的侧壁和终止在侧壁处的栅极氧化物的覆盖部分形成。 用氮化物间隔物完整地进行各向同性氧化物蚀刻。 各向同性蚀刻横向后退氧化物的相对边缘，使得氧化物的宽度小于多晶硅栅极的宽度。 在浮栅晶体管子结构之上形成栅极间电介质，并且在栅极间电介质上形成控制栅极以形成浮栅晶体管。

    Method for forming self-aligned channel implants using a gate poly reverse mask
    6.
    发明授权
    Method for forming self-aligned channel implants using a gate poly reverse mask 失效
    使用栅极多反向掩模形成自对准沟道植入物的方法

    公开(公告)号：US06410394B1

    公开(公告)日：2002-06-25

    申请号：US09465305

    申请日：1999-12-17

    申请人： Kai Shao ,  Yimin Wang ,  Jian Xun Li ,  Shao-Fu Sanford Chu

    发明人： Kai Shao ,  Yimin Wang ,  Jian Xun Li ,  Shao-Fu Sanford Chu

    IPC分类号： H01L21336

    CPC分类号： H01L21/823807 ,  Y10S977/712

    摘要： A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.

    摘要翻译： 一种用于形成具有自对准沟道植入物的CMOS晶体管栅极的方法。 提供具有第一有源区的半导体结构。 在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。 使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。 形成暴露第一通道植入物开口的第一通道植入物掩模。 杂质离子通过第一通道注入开口注入，以形成第一阈值调整区域和第一抗穿通区域。 在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。 去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

    CLOCK RECOVERY FOR MEDIA STREAM IN BURSTY NETWORK CHANNEL
    7.
    发明申请
    CLOCK RECOVERY FOR MEDIA STREAM IN BURSTY NETWORK CHANNEL 审中-公开
    BURSTY网络频道媒体流的时钟恢复

    公开(公告)号：US20150030088A1

    公开(公告)日：2015-01-29

    申请号：US14089701

    申请日：2013-11-25

    申请人： Vincent M. K. Chan ,  Yimin Wang

    发明人： Vincent M. K. Chan ,  Yimin Wang

    IPC分类号： H04N19/86 ,  H04N19/70

    CPC分类号： H04N19/42 ,  H04N19/40

    摘要： A media processing device includes a transmission interface to transmit an output media stream based on an output clock signal, whereby output video stream includes a representation (e.g., a transcoded representation) of an input media stream. The media processing device further includes a clock drift module to generate a stream of average clock drift values representing differences between a local system time clock and clock references of the input media stream and a proportional-integral-derivative (PID) controller to filter the stream of average clock drift values to generate a stream of filtered average clock drift values. The media processing device further includes a clock adjust module to adjust the output clock signal based on the stream of filtered average clock drift values.

    摘要翻译： 媒体处理设备包括：传输接口，用于基于输出时钟信号传输输出媒体流，由此输出视频流包括输入媒体流的表示（例如，转码表示）。 媒体处理设备还包括时钟漂移模块，用于生成表示本地系统时钟与输入媒体流的时钟参考与比例积分微分（PID）控制器之间的差异的平均时钟漂移值流，以过滤流 的平均时钟漂移值，以生成滤波的平均时钟漂移值流。 媒体处理设备还包括时钟调整模块，用于基于滤波的平均时钟漂移值流来调整输出时钟信号。

    Split gate flash cell and method for making the same
    8.
    发明授权
    Split gate flash cell and method for making the same 有权
    分闸门闪存单元及其制作方法

    公开(公告)号：US08921917B2

    公开(公告)日：2014-12-30

    申请号：US14038410

    申请日：2013-09-26

    申请人： Yimin Wang

    发明人： Yimin Wang

    IPC分类号： H01L29/788 ,  H01L27/088 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115

    CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/088 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324

    摘要： A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.

    摘要翻译： 提供了具有浮动栅极晶体管的分离栅极闪存单元器件。 每个浮栅晶体管通过提供浮置晶体管子结构形成，该浮动栅极晶体管子结构包括设置在设置在公共源的一部分上的栅极氧化物上的多晶硅栅极上的氧化物。 氮化物间隔物沿着浮栅晶体管子结构的侧壁和终止在侧壁处的栅极氧化物的覆盖部分形成。 用氮化物间隔物完整地进行各向同性氧化物蚀刻。 各向同性蚀刻横向后退氧化物的相对边缘，使得氧化物的宽度小于多晶硅栅极的宽度。 在浮栅晶体管子结构之上形成栅极间电介质，并且在栅极间电介质上形成控制栅极以形成浮栅晶体管。

    Methods and structures for customized STI structures in semiconductor devices
    9.
    发明授权
    Methods and structures for customized STI structures in semiconductor devices 有权
    半导体器件定制STI结构的方法和结构

    公开(公告)号：US08629514B2

    公开(公告)日：2014-01-14

    申请号：US13008252

    申请日：2011-01-18

    申请人： Yimin Wang

    发明人： Yimin Wang

    IPC分类号： H01L21/02

    CPC分类号： H01L21/76229

    摘要： A method and structure provide for customizing STI, shallow trench isolation, structures in various parts of a system-on-chip, SOC, or other semiconductor integrated circuit device. Within an individual chip, STI structures are formed to include different dielectric thicknesses that are particularly advantageous for the particular device portion of the SOC chip in which the STI structure is formed.

    摘要翻译： 一种方法和结构提供了定制STI，浅沟槽隔离，片上系统，SOC或其他半导体集成电路器件的各个部分中的结构。 在单个芯片内，STI结构形成为包括对形成STI结构的SOC芯片的特定器件部分特别有利的不同介电厚度。

    Flash cell with floating gate transistors formed using spacer technology
    10.
    发明授权
    Flash cell with floating gate transistors formed using spacer technology 有权
    使用间隔技术形成浮栅晶体管的闪存单元

    公开(公告)号：US08389356B2

    公开(公告)日：2013-03-05

    申请号：US13045449

    申请日：2011-03-10

    申请人： Yimin Wang

    发明人： Yimin Wang

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  H01L21/28132 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

    摘要： Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.

    摘要翻译： 形成分裂栅极闪存单元结构的方法提供了在形成控制栅极时免于光致抗蚀剂图案的未对准的对称单元。 在闪存单元中使用的浮栅晶体管中使用间隔物来形成浮置栅极。 间隔物可以是用于掩蔽将形成浮动栅极的多晶硅层的氧化物间隔物，或者间隔物可以是本身将形成浮栅的多晶硅间隔物。 浮栅晶体管的栅极间氧化物可以使用HTO形成或者可以沉积。 硬掩模间隔件与控制栅光致抗蚀剂图案化操作结合使用以控制控制栅极的尺寸和配置以及沟道长度。