公开(公告)号：US08410818B1

公开(公告)日：2013-04-02

申请号：US13372978

申请日：2012-02-14

申请人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： H03K19/094

CPC分类号： H03K3/012 ,  H03K19/0013 ,  H03K19/018521

摘要： A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

公开(公告)号：US20120262209A1

公开(公告)日：2012-10-18

申请号：US13089160

申请日：2011-04-18

申请人： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03K5/15066 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/06

摘要： An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.

摘要翻译： 实施例是集成电路。 集成电路包括时钟发生器和数据传输线。 时钟发生器产生时钟信号。 至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。 至少部分地通过至少一个时钟信号来触发每个数据传输线。

公开(公告)号：US08482332B2

公开(公告)日：2013-07-09

申请号：US13089160

申请日：2011-04-18

申请人： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： H03K3/00

CPC分类号： H03K5/15066 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/06

摘要： An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.

摘要翻译： 实施例是集成电路。 集成电路包括时钟发生器和数据传输线。 时钟发生器产生时钟信号。 至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。 至少部分地通过至少一个时钟信号来触发每个数据传输线。

公开(公告)号：US08510701B2

公开(公告)日：2013-08-13

申请号：US13350894

申请日：2012-01-16

申请人： Chen-Ting Ko ,  Chih-Hsien Chang ,  Yung-Chow Peng

发明人： Chen-Ting Ko ,  Chih-Hsien Chang ,  Yung-Chow Peng

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.

摘要翻译： 本公开的一些方面提供了电子设计自动化（EDA）技术，其在设计期间检查诸如晶体管或其他半导体器件的各个块是否连接到其正确的电源域。 以这种方式，所公开的EDA技术可以限制或防止在制造时应用于块的过应力条件并有助于提高集成电路的可靠性。

公开(公告)号：US08762897B2

公开(公告)日：2014-06-24

申请号：US13475853

申请日：2012-05-18

申请人： Chih-Hsien Chang ,  Yung-Chow Peng ,  Fu-Lung Hsueh

发明人： Chih-Hsien Chang ,  Yung-Chow Peng ,  Fu-Lung Hsueh

IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00 ,  G06F19/00

CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F17/5009 ,  G06F17/5045 ,  G06F17/5068 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

摘要： A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.

摘要翻译： 电路设计系统包括被配置为产生电路的示意图信息和预着色信息的示意性设计工具。 电路设计系统还包括被配置为在非暂时计算机可读介质上存储原理图信息和预着色信息的网表文件，以及被配置为从网表文件中提取预着色信息的提取工具。 包括在电路设计系统中的布局设计工具被配置为基于原理图信息和预着色信息设计至少一个掩模。 电路设计系统还包括布局与示意性比较工具，其被配置为将至少一个掩模与示意图信息和预着色信息进行比较。

公开(公告)号：US20130185688A1

公开(公告)日：2013-07-18

申请号：US13350894

申请日：2012-01-16

申请人： Chen-Ting Ko ,  Chih-Hsien Chang ,  Yung-Chow Peng

发明人： Chen-Ting Ko ,  Chih-Hsien Chang ,  Yung-Chow Peng

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.

摘要翻译： 本公开的一些方面提供了电子设计自动化（EDA）技术，其在设计期间检查诸如晶体管或其他半导体器件的各个块是否连接到其正确的电源域。 以这种方式，所公开的EDA技术可以限制或防止在制造时应用于块的过应力条件并有助于提高集成电路的可靠性。

公开(公告)号：US08719755B2

公开(公告)日：2014-05-06

申请号：US13562638

申请日：2012-07-31

申请人： Wen-Shen Chou ,  Yung-Chow Peng ,  Chih-Chiang Chang ,  Chin-Hua Wen

发明人： Wen-Shen Chou ,  Yung-Chow Peng ,  Chih-Chiang Chang ,  Chin-Hua Wen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

摘要翻译： 除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。 例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。 在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。 例如，第一图案密度和第二图案密度是门密度和/或多密度。 为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。 以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。

公开(公告)号：US08378742B2

公开(公告)日：2013-02-19

申请号：US12987464

申请日：2011-01-10

申请人： Renjeng Chiang ,  Yung-Chow Peng

发明人： Renjeng Chiang ,  Yung-Chow Peng

IPC分类号： H01L25/00

CPC分类号： H01L27/0207 ,  H01L23/4824 ,  H01L23/5286 ,  H01L23/5329 ,  H01L24/05 ,  H01L27/092 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00

摘要： A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two.

摘要翻译： 一种用于半导体芯片的驱动器，该驱动器具有带有第一端和第二端的漏极线以及分别具有源极，栅极和漏极的p型和n型晶体管。 连接到正电源线的p型晶体管的源极，连接到地电源线的n型晶体管的源极。 分别连接到第一和第二输入信号的p型和n型晶体管的栅极。 连接到漏极线的p型和n型晶体管的漏极。 p型和n型晶体管被布置成使得连接到漏极线的n个晶体管的数量与在漏极线的第一端之间连接到漏极线的多个p型晶体管之间的差异与所有距离 漏极线小于2。

公开(公告)号：US06593775B2

公开(公告)日：2003-07-15

申请号：US09761930

申请日：2001-01-17

申请人： Kou-Hwa Yu ,  Jui-Chiang Wang ,  Yung-Chow Peng

发明人： Kou-Hwa Yu ,  Jui-Chiang Wang ,  Yung-Chow Peng

IPC分类号： H03K19185

CPC分类号： G06F1/32 ,  G06F1/26

摘要： This invention relates to an insulator for a multi-power system, which is used to resolve the current leakage which comes from each power supplied to the corresponding devices which are not being correctly operated. The isolating device includes: a first power supply for providing an operating power to the isolating device; a level detector for detecting the voltage level of the operating power; a signal isolation controller for changing the output level of the circuit supplied by the operating power based on the operating power detected; and a second power for supplying a real-time power to circuit for power saving operation based on the changed output level.

公开(公告)号：US06473282B1

公开(公告)日：2002-10-29

申请号：US09547186

申请日：2000-04-11

申请人： Shi-Tron Lin ,  Ta-Lee Yu ,  Yung-Chow Peng

发明人： Shi-Tron Lin ,  Ta-Lee Yu ,  Yung-Chow Peng

IPC分类号： H02H320

CPC分类号： H01L27/0251

摘要： A latch-up protection circuit for an integrated circuit powered through a first power rail and a second power rail is disclosed, the integrated circuit having at least one semiconductor bulk of a conductivity type. The latch-up protection circuit comprises a control circuit and a switch circuit. The control circuit is connected to the first power rail and the second power rail for detecting a relative voltage therebetween and generating a first control signal and a second control signal. The switch circuit connected to the first power rail and the control circuit. When the relative voltage is greater than a first predetermined value, the switch circuit in response to the first control signal electrically connects the first power rail with the at least one semiconductor bulk. When the relative voltage is smaller than the first predetermined value, the switch in response to the first control signal electrically disconnects the first power rail from the at least one semiconductor bulk.

摘要翻译： 公开了一种用于通过第一电力轨道和第二电力轨道供电的集成电路的闩锁保护电路，该集成电路具有至少一个导电类型的半导体本体。 闩锁保护电路包括控制电路和开关电路。 控制电路连接到第一电源轨和第二电源轨，用于检测它们之间的相对电压，并产生第一控制信号和第二控制信号。 开关电路连接到第一电源轨和控制电路。 当相对电压大于第一预定值时，响应于第一控制信号的开关电路将第一电源轨与至少一个半导体块电连接。 当相对电压小于第一预定值时，响应于第一控制信号的开关将第一电力轨与至少一个半导体块电气断开。