CMOS dual metal gate semiconductor device
    1.
    发明授权
    CMOS dual metal gate semiconductor device 有权
    CMOS双金属栅极半导体器件

    公开(公告)号:US08836038B2

    公开(公告)日:2014-09-16

    申请号:US12883241

    申请日:2010-09-16

    摘要: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

    摘要翻译: 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层,其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

    EDDY CURRENT BASED METHOD FOR COATING THICKNESS MEASUREMENT
    2.
    发明申请
    EDDY CURRENT BASED METHOD FOR COATING THICKNESS MEASUREMENT 有权
    用于涂层厚度测量的基于EDDY电流的方法

    公开(公告)号:US20130132012A1

    公开(公告)日:2013-05-23

    申请号:US13298887

    申请日:2011-11-17

    IPC分类号: G06F19/00

    摘要: A method of configuring an eddy current detector to measure a thickness of a coating on a substrate includes measuring an impedance of the coated substrate, and establishing an impendence plane plot using a computer. The method may also include determining a rotation angle. The rotation angle may be an angle of rotation of the impedance plane plot that will make the inductive reactance component of the impedance substantially insensitive to substrate electrical conductivity within a coating thickness range. The method may further include establishing a calibration curve that is substantially insensitive to substrate electrical conductivity using the rotation angle. The calibration curve may be a curve that relates the inductive reactance component of the impedance to coating thickness.

    摘要翻译: 配置涡流检测器以测量衬底上的涂层的厚度的方法包括测量涂覆的衬底的阻抗,以及使用计算机建立阻抗平面图。 该方法还可以包括确定旋转角度。 旋转角度可以是阻抗平面图的旋转角度,其将使得阻抗的感抗分量对涂层厚度范围内的基板导电性基本上不敏感。 该方法可以进一步包括使用旋转角度建立对衬底导电性基本上不敏感的校准曲线。 校准曲线可以是将阻抗的感抗分量与涂层厚度相关联的曲线。

    Semiconductor devices and methods with bilayer dielectrics
    3.
    发明授权
    Semiconductor devices and methods with bilayer dielectrics 有权
    具有双层电介质的半导体器件和方法

    公开(公告)号:US08384159B2

    公开(公告)日:2013-02-26

    申请号:US12426477

    申请日:2009-04-20

    摘要: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.

    摘要翻译: 公开了一种半导体器件,包括:衬底; 形成在所述衬底上并由第一高k材料形成的第一介电层,所述第一高k材料选自HfO 2,HfSiO,HfSiON,HfTaO,HfTiO,HfTiTaO,HfAlON和HfZrO; 形成在所述第一介电层上并由第二高k材料形成的第二介电层,所述第二高k材料不同于所述第一高k材料并选自HfO 2,HfSiO,HfSiON,HfTaO, HfTiO,HfTiTaO,HfAlON和HfZrO; 以及形成在第二介电层上的金属栅极。 第一电介质层包括选自N,O和Si的离子。

    LED based omni-directional light engine
    4.
    发明授权
    LED based omni-directional light engine 失效
    LED全方位光引擎

    公开(公告)号:US08287147B2

    公开(公告)日:2012-10-16

    申请号:US12462259

    申请日:2009-07-31

    摘要: An LED based omni-directional light engine includes a toroidal lens coupled to a controller circuit board and two or more evenly spaced LEDs mounted to the controller circuit board. The toroidal lens includes an inner surface coated with a layer of reflection materials, an outer surface, and a flat base surface. The controller circuit board is electrically coupled to a power source. The LEDs are located immediately under the flat base surface. The inner surface substantially reflects light beams emitted from the LEDs to the outer surface which refracts the beams to the omni-directions.

    摘要翻译: 基于LED的全向光引擎包括耦合到控制器电路板的环形透镜和安装到控制器电路板的两个或更多个均匀分布的LED。 环形透镜包括涂覆有反射材料层,外表面和平坦基底表面的内表面。 控制器电路板电耦合到电源。 LED位于平坦的基面正下方。 内表面基本上反射从LED发射的光束到将整个光束向全方位折射的外表面。

    Zinc Oxide Sulfur Sensor Measurement System
    5.
    发明申请
    Zinc Oxide Sulfur Sensor Measurement System 有权
    氧化锌硫传感器测量系统

    公开(公告)号:US20120174656A1

    公开(公告)日:2012-07-12

    申请号:US13354821

    申请日:2012-01-20

    IPC分类号: G01N33/00

    CPC分类号: G01N33/287

    摘要: A measurement system is disclosed for determining a sulfur concentration in a liquid, such as a liquid fuel. The measurement system includes a first electrode that is at least partially coated with zinc oxide and, more specifically, zinc oxide microstructures. The zinc oxide microstructures have a crystal lattice structure that is oriented in the (002) plane. The first electrode may be connected to an electrometer which, in turn, may be connected to a second electrode. The second electrode may be disposed on a common substrate with the first electrode or may be in the form of a plate disposed substantially parallel to the first electrode.

    摘要翻译: 公开了一种用于测定诸如液体燃料的液体中的硫浓度的测量系统。 测量系统包括至少部分地涂覆有氧化锌的第一电极,更具体地,氧化锌微结构。 氧化锌微结构具有在(002)面取向的晶格结构。 第一电极可以连接到静电计,静电计又可以连接到第二电极。 第二电极可以设置在具有第一电极的公共衬底上,或者可以是基本上平行于第一电极设置的板的形式。

    Implantation method for reducing threshold voltage for high-K metal gate device
    7.
    发明授权
    Implantation method for reducing threshold voltage for high-K metal gate device 有权
    用于降低高K金属栅极器件的阈值电压的植入方法

    公开(公告)号:US07994051B2

    公开(公告)日:2011-08-09

    申请号:US12253741

    申请日:2008-10-17

    IPC分类号: H01L21/00

    摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.

    摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质层,在高k电介质层上形成覆盖层,在覆盖层上形成金属层,在金属层上形成半导体层,对金属层进行注入工艺 半导体层,使用包括F的物质的注入工艺,以及从包括高k电介质层,覆盖层,金属层和半导体层的多个层形成栅极结构。

    Led based precision approach path indicator
    8.
    发明申请
    Led based precision approach path indicator 失效
    基于LED的精密进近路径指示器

    公开(公告)号:US20100123398A1

    公开(公告)日:2010-05-20

    申请号:US12590771

    申请日:2009-11-12

    IPC分类号: H05B37/00 F21V1/00 G01B11/26

    CPC分类号: G01B11/26 H05B33/0803

    摘要: A precision approach path indicator system (PAPI) including multiple LHA indicators and power sources. Each LHA indicator comprises several assembly modules, with each module made up of several red and white LEDs, several collimating lens, one optical combiner, and one projection lens set. From a side view of the module, the red LEDs are placed on top of white LEDs, with a collimating lens in front of each LED. The optical combiner is in front of both the red and white LEDs, slightly above the white LEDs in vertical placement. The optical combiner has a reflective coating on the bottom surface, and a red light filter coating on the projection surface. The combined beam of light is projected out through a projection lens at front of the assembly module.

    摘要翻译: 精密进场路径指示系统(PAPI),包括多个LHA指示灯和电源。 每个LHA指示器包括多个组装模块,每个模块由几个红色和白色LED组成,几个准直透镜,一个光学组合器和一个投影透镜组。 从模块的侧视图,红色LED放置在白色LED的顶部,每个LED前面有准直透镜。 光学组合器位于红色和白色LED的前面,垂直放置时略高于白色LED。 光学组合器在底表面上具有反射涂层,并且在投影表面上具有红色光过滤器涂层。 组合的光束通过组装模块前面的投影透镜突出出来。

    METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS
    9.
    发明申请
    METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS 有权
    在门过程中形成金属门的方法

    公开(公告)号:US20100081262A1

    公开(公告)日:2010-04-01

    申请号:US12411546

    申请日:2009-03-26

    摘要: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

    摘要翻译: 本公开提供一种制造半导体器件的方法,其包括提供具有第一区域和第二区域的衬底,分别在第一和第二区域中形成第一和第二栅极堆叠,第一栅极堆叠包括第一虚拟栅极和 所述第二栅极堆叠包括第二伪栅极,去除所述第一栅极堆叠中的所述第一伪栅极,从而形成第一沟槽并且去除所述第二栅极堆叠中的所述第二伪栅极,从而形成第二沟槽,从而形成第一栅极堆叠中的第一金属层 沟槽,并且在第二沟槽中,去除第一沟槽中的第一金属层的至少一部分,在第一沟槽的其余部分和第二沟槽的其余部分中形成第二金属层,回流第二金属层,以及 进行化学机械抛光(CMP)。

    NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING
    10.
    发明申请
    NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING 审中-公开
    新型高K金属结构及其制备方法

    公开(公告)号:US20100044804A1

    公开(公告)日:2010-02-25

    申请号:US12427222

    申请日:2009-04-21

    IPC分类号: H01L29/78 H01L21/28

    摘要: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.

    摘要翻译: 本公开提供了一种半导体器件,其包括半导体衬底,形成在衬底中的晶体管,晶体管包括形成在衬底上的高k栅极电介质,高k栅极电介质具有从一个侧壁到 高k栅极电介质的另一个侧壁和形成在高k栅极电介质上的金属栅极,金属栅极具有从金属栅极的一个侧壁到另一侧壁测量的第二长度,第二长度小于 第一长。