公开(公告)号：US06198122B1

公开(公告)日：2001-03-06

申请号：US09025908

申请日：1998-02-19

申请人： Mariko Habu ,  Yusuke Kohyama ,  Toru Ozaki ,  Keiji Hosotani

发明人： Mariko Habu ,  Yusuke Kohyama ,  Toru Ozaki ,  Keiji Hosotani

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L27/10852

摘要： A semiconductor memory includes a semiconductor substrate, a memory cell portion formed on the substrate and including stacked capacitors formed on the substrate, each having a storage electrode formed on a bottom surface of a recess in an insulating layer, a capacitor insulating film formed on the storage electrode, and a plate electrode formed on the capacitor insulating film and lower than an upper edge of the recess, and a first multilayered interconnecting layer having an interconnecting layer including a plate interconnection connected to the plate electrode, and a peripheral circuit portion formed adjacent to the memory cell portion on the substrate and comprising a second multilayered interconnecting layer. The plate interconnection includes a portion so formed as to bury the recess and connected to the plate electrode, and the second multilayered interconnecting layer includes an interconnecting layer having an upper surface substantially leveled with an upper surface of the interconnecting layer including the plate interconnection of the first multilayered interconnecting layer.

摘要翻译： 半导体存储器包括半导体衬底，形成在衬底上的存储单元部分，并且包括形成在衬底上的叠层电容器，每个存储电极形成在绝缘层凹部的底表面上的存储电极，形成在绝缘层上的电容器绝缘膜 存储电极和形成在电容器绝缘膜上并低于凹部的上边缘的平板电极，以及具有互连层的第一多层互连层，所述互连层包括连接到平板电极的板状互连层，以及形成在邻接 到基板上的存储单元部分并且包括第二多层互连层。 板互连包括形成为埋入凹部并连接到平板电极的部分，并且第二多层互连层包括互连层，该互连层具有基本上与互连层的上表面大致平齐的互连层，包括互连层的板互连 第一多层互连层。

公开(公告)号：US06362042B1

公开(公告)日：2002-03-26

申请号：US09664773

申请日：2000-09-19

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L28/55 ,  H01L28/82 ,  H01L28/90

摘要： Provided is a semiconductor device and a method of manufacturing the semiconductor device having a stacked type capacitor excellent in storage capacity, breakdown voltage and reliability. A storage node electrode (Ru) of the stacked-type capacitor is formed on a contact hole of the underlying insulating film by the steps of forming the side wall of the contact hole diagonally at a taper angle within the range of 90 to 110°, forming a storage node electrode on the inner wall surface of the contact hole, filling SOG in the contact hole, etching off the Ru film on the insulating film using SOG as a mask, and etching off the Ru film formed on the upper peripheral region of the inner wall in the depth direction of the contact hole. Thereafter, the dielectric film of the stacked-type capacitor formed of a (Ba, Sr) TiO3 thin film is formed on the Ru storage node electrode. In this manner, it is possible to obtain a stack-type capacitor having a drastically-improved step coverage and a high breakdown voltage. In addition, it is easy to reduce the distance between adjacent Ru storage node electrodes within a resolution limit of lithography, compared to the conventional method.

摘要翻译： 提供一种半导体器件和制造具有存储容量，击穿电压和可靠性优异的堆叠型电容器的半导体器件的方法。 层叠型电容器的存储节点电极（Ru）通过以下步骤形成在下面的绝缘膜的接触孔上：将接触孔的侧壁对角地形成在90°至110°的范围内的锥角， 在接触孔的内壁表面上形成存储节点电极，在接触孔中填充SOG，使用SOG作为掩模蚀刻绝缘膜上的Ru膜，并且蚀刻形成在上部周边区域上的Ru膜 接触孔深度方向的内壁。 此后，在Ru储存节点电极上形成由（Ba，Sr）TiO 3薄膜形成的层叠型电容器的电介质膜。 以这种方式，可以获得具有急剧改善的台阶覆盖和高击穿电压的堆叠型电容器。 此外，与常规方法相比，在光刻的分辨率极限内容易地减小相邻Ru存储节点电极之间的距离。

公开(公告)号：US06333538B1

公开(公告)日：2001-12-25

申请号：US09388937

申请日：1999-09-02

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

摘要翻译： 在制造COB DRAM单元的方法中，在与栅电极自对准的源极和漏极上形成多晶硅插塞。 在多晶硅插塞上形成位线接触和存储电极接触，从而减小位线接触和存储电极接触的纵横比。 由于多晶硅插塞形成与栅极电极自对准，不会发生相邻元件区域的触点短路和源极和漏极的插头短路，从而导致高度的不对准保护。 此外，不需要独立的光刻工艺来形成多晶硅插塞，因此，制造步骤的数量减少。

公开(公告)号：US06175130B1

公开(公告)日：2001-01-16

申请号：US09447813

申请日：1999-11-23

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L28/55 ,  H01L28/82 ,  H01L28/90

摘要： Provided is a semiconductor device and a method of manufacturing the semiconductor device having a stacked type capacitor excellent in storage capacity, breakdown voltage and reliability. A storage node electrode (Ru) of the stacked-type capacitor is formed on a contact hole of the underlying insulating film by the steps of forming the side wall of the contact hole diagonally at a taper angle within the range of 90 to 110°, forming a storage node electrode on the inner wall surface of the contact hole, filling SOG in the contact hole, etching off the Ru film on the insulating film using SOG as a mask, and etching off the Ru film formed on the upper peripheral region of the inner wall in the depth direction of the contact hole. Thereafter, the dielectric film of the stacked-type capacitor formed of a (Ba, Sr) TiO3 thin film is formed on the Ru storage node electrode. In this manner, it is possible to obtain a stack-type capacitor having a drastically-improved step coverage and a high breakdown voltage. In addition, it is easy to reduce the distance between adjacent Ru storage node electrodes within a resolution limit of lithography, compared to the conventional method.

摘要翻译： 提供一种半导体器件和制造具有存储容量，击穿电压和可靠性优异的堆叠型电容器的半导体器件的方法。 层叠型电容器的存储节点电极（Ru）通过以下步骤形成在下面的绝缘膜的接触孔上：将接触孔的侧壁对角地形成在90°至110°的范围内的锥角， 在接触孔的内壁表面上形成存储节点电极，在接触孔中填充SOG，使用SOG作为掩模蚀刻绝缘膜上的Ru膜，并且蚀刻形成在上部周边区域上的Ru膜 接触孔深度方向的内壁。 此后，在Ru储存节点电极上形成由（Ba，Sr）TiO 3薄膜形成的层叠型电容器的电介质膜。 以这种方式，可以获得具有急剧改善的台阶覆盖和高击穿电压的堆叠型电容器。 此外，与常规方法相比，在光刻的分辨率极限内容易地减小相邻Ru存储节点电极之间的距离。

公开(公告)号：US06593202B2

公开(公告)日：2003-07-15

申请号：US09909790

申请日：2001-07-23

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L2120

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

摘要翻译： 在制造COB DRAM单元的方法中，在与栅电极自对准的源极和漏极上形成多晶硅插塞。 在多晶硅插塞上形成位线接触和存储电极接触，从而减小位线接触和存储电极接触的纵横比。 由于多晶硅插塞形成与栅极电极自对准，不会发生相邻元件区域的触点短路和源极和漏极的插头短路，从而导致高度的不对准保护。 此外，不需要独立的光刻工艺来形成多晶硅插塞，因此，制造步骤的数量减少。

公开(公告)号：US5977583A

公开(公告)日：1999-11-02

申请号：US684059

申请日：1996-07-19

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

摘要翻译： 在制造COB DRAM单元的方法中，在与栅电极自对准的源极和漏极上形成多晶硅插塞。 在多晶硅插塞上形成位线接触和存储电极接触，从而减小位线接触和存储电极接触的纵横比。 由于多晶硅插塞形成与栅极电极自对准，不会发生相邻元件区域的触点短路和源极和漏极的插头短路，从而导致高度的不对准保护。 此外，不需要独立的光刻工艺来形成多晶硅插塞，因此，制造步骤的数量减少。

公开(公告)号：US6051859A

公开(公告)日：2000-04-18

申请号：US8491

申请日：1998-01-16

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L28/82 ,  H01L28/55 ,  H01L28/90

摘要： Provided is a semiconductor device and a method of manufacturing the semiconductor device having a stacked type capacitor excellent in storage capacity, breakdown voltage and reliability. A storage node electrode (Ru) of the stacked-type capacitor is formed on a contact hole of the underlying insulating film by the steps of forming the side wall of the contact hole diagonally at a taper angle within the range of 90 to 110.degree., forming a storage node electrode on the inner wall surface of the contact hole, filling SOG in the contact hole, etching off the Ru film on the insulating film using SOG as a mask, and etching off the Ru film formed on the upper peripheral region of the inner wall in the depth direction of the contact hole. Thereafter, the dielectric film of the stacked-type capacitor formed of a (Ba, Sr) TiO.sub.3 thin film is formed on the Ru storage node electrode. In this manner, it is possible to obtain a stack-type capacitor having a drastically-improved step coverage and a high breakdown voltage. In addition, it is easy to reduce the distance between adjacent Ru storage node electrodes within a resolution limit of lithography, compared to the conventional method.

摘要翻译： 提供一种半导体器件和制造具有存储容量，击穿电压和可靠性优异的堆叠型电容器的半导体器件的方法。 层叠型电容器的存储节点电极（Ru）通过以下步骤形成在下面的绝缘膜的接触孔上：将接触孔的侧壁对角地成90度到110度的锥角， 在接触孔的内壁表面上形成存储节点电极，在接触孔中填充SOG，使用SOG作为掩模蚀刻绝缘膜上的Ru膜，并且蚀刻形成在上部周边区域上的Ru膜 接触孔深度方向的内壁。 此后，在Ru储存节点电极上形成由（Ba，Sr）TiO 3薄膜形成的层叠型电容器的电介质膜。 以这种方式，可以获得具有急剧改善的台阶覆盖和高击穿电压的堆叠型电容器。 此外，与常规方法相比，在光刻的分辨率极限内容易地减小相邻Ru存储节点电极之间的距离。

公开(公告)号：US08111538B2

公开(公告)日：2012-02-07

申请号：US12273874

申请日：2008-11-19

申请人： Keiji Hosotani ,  Yoshiaki Asao ,  Yoshihisa Iwata

发明人： Keiji Hosotani ,  Yoshiaki Asao ,  Yoshihisa Iwata

IPC分类号： G11C11/00

CPC分类号： G11C7/20 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C29/028 ,  G11C29/50 ,  G11C2013/0083 ,  G11C2029/1206 ,  G11C2029/5002 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data. An allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched when a power source is turned on.

摘要翻译： 半导体存储器件包括具有根据“0”数据/“1”数据被设置成低电阻状态/高电阻状态的多个存储器单元的存储单元阵列。 当电源接通时，切换“0”数据/“1”数据和低电阻状态/高电阻状态的分配。

公开(公告)号：US07932513B2

公开(公告)日：2011-04-26

申请号：US12043617

申请日：2008-03-06

申请人： Keiji Hosotani ,  Yoshiaki Asao ,  Toshihiko Nagase

发明人： Keiji Hosotani ,  Yoshiaki Asao ,  Toshihiko Nagase

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L39/00

CPC分类号： G11C11/16 ,  B82Y10/00 ,  G11C11/1675 ,  H01L27/22 ,  H01L27/228 ,  H01L43/08

摘要： A magnetic random access memory includes a bit line running in a first direction, a first word line running in a second direction different from the first direction, and a memory element having a magnetoresistive effect element including a fixed layer having a fixed magnetization direction, a recording layer having a reversible magnetization direction, and a nonmagnetic layer formed between the fixed layer and the recording layer, the magnetization directions in the fixed layer and the recording layer being perpendicular to a film surface, and a heater layer in contact with the magnetoresistive effect element, the memory element being connected to the bit line, and formed to oppose a side surface of the first word line such that the memory element is insulated from the first word line.

摘要翻译： 磁性随机存取存储器包括沿第一方向运行的位线，沿与第一方向不同的第二方向运行的第一字线，以及具有包括具有固定磁化方向的固定层的磁阻效应元件的存储元件， 具有可逆磁化方向的记录层和形成在固定层和记录层之间的非磁性层，固定层和记录层中的磁化方向垂直于膜表面，以及与磁阻效应接触的加热器层 所述存储元件连接到所述位线，并形成为与所述第一字线的侧表面相对，使得所述存储元件与所述第一字线绝缘。

公开(公告)号：US07706175B2

公开(公告)日：2010-04-27

申请号：US11839265

申请日：2007-08-15

申请人： Keiji Hosotani ,  Yoshiaki Asao ,  Akihiro Nitayama

发明人： Keiji Hosotani ,  Yoshiaki Asao ,  Akihiro Nitayama

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.

摘要翻译： 磁性随机存取存储器包括第一布线，形成在第一布线上方并与第一布线间隔开的第二布线;形成在与第一布线的上表面接触形成的第一布线和第二布线之间的磁阻效应元件，以及 具有形成在固定层和记录层之间的固定层，记录层和非磁性层，形成在磁阻效应元件上并与磁阻效应元件集成以形成堆叠层的金属层，形成第一侧绝缘膜 在金属层的侧表面，磁阻效应元件和第一布线，与第一侧绝缘膜的侧表面接触形成的第一触点和形成在金属层上的第三布线和第一触点电连接 连接磁阻效应元件和第一触点。