公开(公告)号：US06303429B1

公开(公告)日：2001-10-16

申请号：US09676084

申请日：2000-10-02

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

摘要翻译： 电容器形成在由氧化硅制成的层间绝缘体中制成的沟槽中。 绝缘膜（例如，氮化硅膜）设置在层间绝缘体的每个沟槽的侧面上。 在层间绝缘体的每个沟槽中设置由钌等制成的存储电极。 在存储电极上形成由BSTO等构成的电容绝缘膜。 在电容器绝缘膜上形成由钌等制成的平板电极。 平板电极对所有提供的电容器是共同的。 任何两个相邻的电容器通过层间绝缘体和设置在层间绝缘体的沟槽的侧面上的绝缘膜电隔离。

公开(公告)号：US06635933B2

公开(公告)日：2003-10-21

申请号：US09953306

申请日：2001-09-17

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC分类号： H01L2976

CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

公开(公告)号：US6153476A

公开(公告)日：2000-11-28

申请号：US30127

申请日：1998-02-25

申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumasa Sunouchi

发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumasa Sunouchi

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

公开(公告)号：US06448618B1

公开(公告)日：2002-09-10

申请号：US09640707

申请日：2000-08-18

申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

IPC分类号： H01L27108

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

摘要翻译： 在DRAM中，基于最小设计规则，在半导体衬底上的单元区域中形成多个第一MOSFET，并且在侧壁部分上形成具有侧壁绝缘膜的第一栅极侧壁 每个第一MOSFET的第一栅电极。 在半导体衬底上的外围电路区域中形成至少一个第二MOSFET，并且在第二MOSFET的第二栅电极的侧壁部分上形成具有侧壁绝缘膜的第二栅极侧壁。 能够形成与第一栅电极自对准的精细接触孔的第一MOSFET和能够在抑制短沟道效应的同时充分减轻寄生电阻的第二MOSFET同时形成 基质。

公开(公告)号：US6104052A

公开(公告)日：2000-08-15

申请号：US273573

申请日：1999-03-22

申请人： Tohru Ozaki ,  Yusuke Kohyama

发明人： Tohru Ozaki ,  Yusuke Kohyama

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/72

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/91

摘要： In a DRAM adopting a self-aligned contact structure, an opening portion of predetermined size is formed in advance in an insulation film which surrounds an on-field gate electrode formed on an element isolating insulation film. The on-field gate electrode contacts a gate contact through the opening portion. A contact hole for the gate contact can thus be formed in self-alignment as can be the contact holes for a bit-line contact and an active contact. Consequently, the contact hole for the gate contact reaching the on-field gate can be formed simultaneously with the contact holes for the bit-line contact and active contact, thereby greatly reducing the number of manufacturing steps.

摘要翻译： 在采用自对准接触结构的DRAM中，预先形成围绕形成在元件隔离绝缘膜上的场上栅电极的绝缘膜中的预定尺寸的开口部分。 场电极电极通过开口部分接触栅极接触。 因此，用于栅极接触的接触孔可以自对准地形成，就像位线接触和有源触点的接触孔一样。 因此，到达栅极栅极的接触孔可以与用于位线接触和有源接触的接触孔同时形成，从而大大减少了制造步骤的数量。

公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US20120139024A1

公开(公告)日：2012-06-07

申请号：US13050297

申请日：2011-03-17

申请人： Takayuki TOBA ,  Tohru Ozaki

发明人： Takayuki TOBA ,  Tohru Ozaki

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/11534 ,  H01L29/66825

摘要： In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate.

摘要翻译： 在一个实施例中，非易失性半导体存储器包括存储单元阵列，第一氮化硅膜和第二氮化硅膜。 存储单元阵列包括NAND单元单元。 每个NAND单元单元具有存储单元晶体管，源极选择栅极晶体管和漏极侧选择栅极晶体管。 源极侧选择栅极晶体管以彼此面对的方式设置，并且漏极侧选择栅极晶体管以彼此面对的方式设置。 第一氮化硅膜存在于源极选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。 第二氮化硅膜形成在漏极侧选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。

公开(公告)号：US20100320518A1

公开(公告)日：2010-12-23

申请号：US12869502

申请日：2010-08-26

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/06

CPC分类号： H01L28/60 ,  G11C11/22 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括：晶体管，包括：源极，漏极和栅极; 源极和漏极上的第一和第二插头; 栅极上的第三个插头具有高于第一插头的顶面; 覆盖晶体管和第一至第三插头的层间绝缘膜; 层间绝缘膜上的铁电电容器，其一个电极连接到第一插头; 覆盖铁电电容器和层间绝缘膜的表面的阻挡膜，以防止影响铁电电容器的物质进入其中; 以及设置在第二和第三插头上的第四和第五插头，并且通过形成在阻挡膜中的连接孔与其连接。

公开(公告)号：US07816717B2

公开(公告)日：2010-10-19

申请号：US12020210

申请日：2008-01-25

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L21/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

摘要： A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of the memory cell section, the select transistor including a second gate electrode provided on the semiconductor substrate with the gate insulating film interposed therebetween, and a source and drain provided at both sides of the second gate electrode on the semiconductor substrate, and a third electrode film connected to the source and drain of the select transistor and connected to a bit line via a bit line contact.

摘要翻译： 一种半导体存储器件，包括：半导体衬底; 存储单元部分，包括设置在所述半导体衬底上的存储晶体管，所述存储晶体管包括设置在所述半导体衬底上的栅极绝缘膜之间的第一栅电极，以及设置在所述第一栅电极的两侧的源极和漏极， 所述半导体衬底和设置在所述存储晶体管上方的强电介质电容器，所述强电介质电容器包括连接到所述存储晶体管的源极和漏极中的任一个的第一电极膜，连接到所述漏极和源极中的另一个的第二电极膜 以及设置在第一电极膜和第二电极膜之间的铁电体膜，具有彼此并联连接的存储晶体管和强电介质电容器的存储单元部分; 以及选择晶体管部分，包括设置在存储单元部分的一端的选择晶体管，所述选择晶体管包括设置在半导体衬底上的栅极绝缘膜之间的第二栅电极，以及设置在两侧的源极和漏极 的第二栅极电极，以及连接到选择晶体管的源极和漏极并经由位线接触连接到位线的第三电极膜。

公开(公告)号：US20100163943A1

公开(公告)日：2010-07-01

申请号：US12559358

申请日：2009-09-14

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L28/55

摘要： A memory includes a first interlayer on transistors; a first and second plugs connected to the transistor; ferroelectric capacitors; a second interlayer covering a side surface of the capacitor; a local interconnection connecting the second plug to the upper electrode, wherein two upper electrodes adjacent to each other on the second plug are connected to the second plug, the lower electrodes adjacent to each other on the first plug are connected to the first plug, cell blocks comprising the connected capacitors are arranged, cell blocks adjacent to each other are arranged to be shifted by a half pitch of the local interconnection, a first gap between two capacitors adjacent to each other on the second plug is larger than twice a thickness of the second interlayer, and a second gap between the cell blocks adjacent to each other is smaller than twice the thickness of the second interlayer.

摘要翻译： 存储器包括晶体管上的第一中间层; 连接到所述晶体管的第一和第二插头; 铁电电容器; 覆盖所述电容器的侧表面的第二夹层; 将第二插头连接到上电极的局部互连，其中在第二插头上彼此相邻的两个上电极连接到第二插头，在第一插头上彼此相邻的下电极连接到第一插头单元 包括连接的电容器的块被布置成彼此相邻的单元块被布置成以局部互连的半间距偏移，在第二插头上彼此相邻的两个电容器之间的第一间隙大于 第二中间层和彼此相邻的电池块之间的第二间隙小于第二中间层的厚度的两倍。