公开(公告)号：US07163894B2

公开(公告)日：2007-01-16

申请号：US10927079

申请日：2004-08-27

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

公开(公告)号：US20050023696A1

公开(公告)日：2005-02-03

申请号：US10927079

申请日：2004-08-27

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/3213 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108 ,  H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

公开(公告)号：US20050206002A1

公开(公告)日：2005-09-22

申请号：US11121976

申请日：2005-05-05

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/3213 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108 ,  H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

摘要翻译： 在半导体器件中，在设置在半导体衬底上的氧化硅膜的表面部分中形成布线图案槽。 布线层被埋入布线图案槽中，其间插入阻挡金属膜。 从布线图形槽的各侧壁部选择性地去除阻挡金属膜。 换句话说，阻挡金属膜仅留在布线图案槽的底部。 因此，可以在半导体器件中形成具有在布线图案槽的每个侧壁和布线层的每一侧之间的介电常数低的中空部的镶嵌布线层。

公开(公告)号：US06906419B2

公开(公告)日：2005-06-14

申请号：US09883210

申请日：2001-06-19

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/3213 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108 ,  H01L29/76 ,  H01L29/00

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

公开(公告)号：US07235882B2

公开(公告)日：2007-06-26

申请号：US11121976

申请日：2005-05-05

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L23/52 ,  H01L23/34

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

摘要翻译： 在半导体器件中，在设置在半导体衬底上的氧化硅膜的表面部分中形成布线图案槽。 布线层被埋入布线图案槽中，其间插入阻挡金属膜。 从布线图形槽的各侧壁部选择性地去除阻挡金属膜。 换句话说，阻挡金属膜仅留在布线图案槽的底部。 因此，可以在半导体器件中形成具有在布线图案槽的每个侧壁和布线层的每一侧之间的介电常数低的中空部的镶嵌布线层。

公开(公告)号：US06222722B1

公开(公告)日：2001-04-24

申请号：US09283280

申请日：1999-04-01

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01G4008

CPC分类号： H01L28/82 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/86 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91

摘要： This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an insulating interlayer having a contact plug. The capacitor has a lower electrode whose inner and outer surfaces are rough or undulated such that one surface has a shape conforming to the shape of the other surface, a dielectric film formed to cover the surfaces of the lower electrode, and an upper electrode formed to cover the lower electrode via the dielectric film. The lower electrode has a cylindrical shape with an open upper end. The lower electrode is connected to a cell transistor through the contact plug. The lower electrode is formed from a metal or a metal oxide.

公开(公告)号：US06197675B1

公开(公告)日：2001-03-06

申请号：US09456990

申请日：1999-12-07

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L2144

CPC分类号： H01L27/10844 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/10852

摘要： A semiconductor memory device comprises a semiconductor substrate, a first conducting layer formed above the main surface of the semiconductor substrate, a second conducting layer formed above the first conducting layer through a first insulating layer and connected to the first conducting layer through a first via-conductor formed in a first contact hole formed in the first insulating layer, and a third conducting layer formed beneath the second conducting layer through a second insulating layer and connected to the second conducting layer through a second via-conductor formed in a second contact hole formed in the second insulating layer, in which an angle formed by a tangent to an inner wall of the first contact hole and a normal to the first conducting layer at a portion of the first conducting layer at which the first contact hole is in contact with the first conducting layer, is larger than an angle formed by a tangent to an inner wall of the second contact hole and a normal to the third conducting layer at a portion of the third conducting layer at which the second contact hole is in contact with the third conducting layer. By virtue of this structure, it is possible to avoid influence of electrical potential variation upon the first conducting layer in the manufacturing process.

摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底的主表面上的第一导电层，通过第一绝缘层形成在第一导电层上方的第二导电层，并通过第一通孔连接到第一导电层， 导体，形成在形成在第一绝缘层中的第一接触孔中，以及第三导电层，其通过第二绝缘层形成在第二导电层的下方，并通过形成在形成的第二接触孔中的第二通孔导体连接到第二导电层 在所述第二绝缘层中，所述第一接触孔与所述第一接触孔的内壁的切线形成的角度与所述第一导电层的所述第一导电层的与所述第一导电层接触的部分的垂直方向 第一导电层大于由与第二接触孔的内壁的切线形成的角度，并且与由垂直于第二接触孔的法线成正比 在第三导电层的第二接触孔与第三导电层接触的部分处的第三导电层。 由于这种结构，在制造过程中可以避免电势变化对第一导电层的影响。

公开(公告)号：US07615813B2

公开(公告)日：2009-11-10

申请号：US11859388

申请日：2007-09-21

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/8234

CPC分类号： H01L23/5252 ,  H01L21/76229 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

摘要翻译： 在硅衬底内同时形成用于元件隔离的第一凹部，用于对准标记的第二凹部和用于反熔丝部的第三凹部。 在整个表面上形成氧化硅膜之后，去除位于第二和第三凹部内的氧化硅膜。 然后，在整个表面上形成栅极绝缘膜，然后在栅极绝缘膜上形成多晶硅膜。 此外，选择性地去除这些多晶硅膜和栅极绝缘膜，以在元件区域上方形成栅电极，在第二凹部中形成对准标记部分，在第三凹部的底表面上形成用于反熔丝部分的栅电极 一部分。

公开(公告)号：US20080012057A1

公开(公告)日：2008-01-17

申请号：US11859388

申请日：2007-09-21

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L29/94

CPC分类号： H01L23/5252 ,  H01L21/76229 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

摘要翻译： 在硅衬底内同时形成用于元件隔离的第一凹部，用于对准标记的第二凹部和用于反熔丝部的第三凹部。 在整个表面上形成氧化硅膜之后，去除位于第二和第三凹部内的氧化硅膜。 然后，在整个表面上形成栅极绝缘膜，然后在栅极绝缘膜上形成多晶硅膜。 此外，选择性地去除这些多晶硅膜和栅极绝缘膜，以在元件区域上方形成栅电极，在第二凹部中形成对准标记部分，在第三凹部的底表面上形成用于反熔丝部分的栅电极 一部分。

公开(公告)号：US06403444B2

公开(公告)日：2002-06-11

申请号：US09800915

申请日：2001-03-08

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L2120

CPC分类号： H01L28/82 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/86 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91

摘要： This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an insulating interlayer having a contact plug. The capacitor has a lower electrode whose inner and outer surfaces are rough or undulated such that one surface has a shape conforming to the shape of the other surface, a dielectric film formed to cover the surfaces of the lower electrode, and an upper electrode formed to cover the lower electrode via the dielectric film. The lower electrode has a cylindrical shape with an open upper end. The lower electrode is connected to a cell transistor through the contact plug. The lower electrode is formed from a metal or a metal oxide.

摘要翻译： 本发明提供一种电容器及其制造方法，该电容器包括具有波状形状和改善的电极面积的金属下电极。 用于数据存储的电容器经由具有接触插塞的绝缘夹层形成在半导体衬底（未示出）上。 电容器具有内表面和外表面粗糙或起伏的下电极，使得一个表面具有符合另一表面形状的形状，形成为覆盖下电极的表面的电介质膜和形成为 通过电介质膜覆盖下电极。 下电极具有开口上端的圆柱形。 下电极通过接触插头连接到单元晶体管。 下电极由金属或金属氧化物形成。