公开(公告)号：US20090218609A1

公开(公告)日：2009-09-03

申请号：US12465202

申请日：2009-05-13

Applicant: Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

Inventor： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

Abstract: A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

Abstract translation: 半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间 相同列的相邻有效区域。

公开(公告)号：US20060105476A1

公开(公告)日：2006-05-18

申请号：US11319605

申请日：2005-12-29

Applicant: Yeon-Dong Choi ,  Kyoung-Yun Baek

Inventor： Yeon-Dong Choi ,  Kyoung-Yun Baek

IPC: H01L21/66

CPC classification number: H01L22/34 ,  G03F1/44 ,  G03F7/70625 ,  G03F7/7065 ,  Y10S438/942

Abstract: A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of a semiconductor substrate, and forming a plurality of test patterns in scribe regions of the substrate. The scribe regions are defined alongside the device-forming regions and separate the device-forming regions from one another. The test patterns have shapes similar to that of the main patterns. Also, one of the test patterns has a critical dimensions similar to that of the main patterns, and other test patterns have respective critical dimensions that are different from the critical dimension of the main patterns.

Abstract translation: 光致抗蚀剂图案及其制造方法使得易于识别导致工艺缺陷的光刻工艺的特定部分变得容易。 制造光致抗蚀剂图案的方法包括在半导体衬底的器件形成区域中形成具有预定临界尺寸的主图案，并在衬底的划线区域中形成多个测试图案。 划线区域沿着器件形成区域定义并且将器件形成区域彼此分离。 测试图案具有与主图案类似的形状。 此外，其中一个测试图案具有与主图案相似的关键尺寸，其他测试图案具有与主图案的临界尺寸不同的各自的关键尺寸。

公开(公告)号：US20110029936A1

公开(公告)日：2011-02-03

申请号：US12662411

申请日：2010-04-15

Applicant: Kyoung-yun Baek ,  Seong-woon Choi ,  Suk-joo Lee

Inventor： Kyoung-yun Baek ,  Seong-woon Choi ,  Suk-joo Lee

IPC: G06F17/50

CPC classification number: G03F1/54 ,  G03F1/36

Abstract: A method of manufacturing a semiconductor device, and more particularly, a method of generating a layout of a semiconductor device. The method of preparing layout of a semiconductor device may include preparing a design layout including a main pattern; dividing the design layout into a plurality of first pieces of layout; preparing a plurality of second pieces of layout by providing a dummy pattern on each of the plurality of first pieces of layout; preparing a plurality of third pieces of layout by performing an optical proximity correction (OPC) process with respect to each of the plurality of second pieces of layout; and recombining the plurality of third pieces of layout.

Abstract translation: 一种制造半导体器件的方法，更具体地，涉及一种生成半导体器件布局的方法。 准备半导体器件的布局的方法可以包括准备包括主图案的设计布局; 将设计布局划分为多个第一布局; 通过在所述多个第一布局中的每一个上提供虚拟图案来准备多个第二布局; 通过对所述多个第二布局中的每一个执行光学邻近校正（OPC）处理来准备多个第三布局; 并重组多个第三布局。

公开(公告)号：US20100096681A1

公开(公告)日：2010-04-22

申请号：US12654255

申请日：2009-12-15

Applicant: Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

Inventor： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

IPC: H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10888

Abstract: In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

Abstract translation: 在存储器件的6F2单元结构及其制造方法中，多个有源区可以在两端部具有第一区域，在中心部分可以具有第二区域。 位线接触焊盘的一部分可以位于第二区域上，另一部分可以位于基板的不与多个有源区域重叠的第三区域上。 位线可以与第三区域的位线接触焊盘连接。 尽管6F2结构的单元电池，电池结构也可以更容易地形成。 多个有源区域可以具有包括主轴和短轴的椭圆形状。 多个有源区域可以被定位在长轴方向上，从而形成有源行，并且可以以这样的结构定位在短轴方向上，使得多个有源区域的中心与相邻的活动区域的中心 相邻活动行中的区域。

公开(公告)号：US20060076599A1

公开(公告)日：2006-04-13

申请号：US11246594

申请日：2005-10-06

Applicant: Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

Inventor： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

IPC: H01L21/8238 ,  H01L29/94

CPC classification number: H01L27/11502 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855

Abstract: A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

公开(公告)号：US20150302135A1

公开(公告)日：2015-10-22

申请号：US14690227

申请日：2015-04-17

Applicant: Chul-Hong PARK ,  Sang-Hoon BAEK ,  Su-Hyeon KIM ,  Kyoung-Yun BAEK ,  Sung-Wook AHN ,  Sang-Kyu OH ,  Seung-Jae JUNG

Inventor： Chul-Hong PARK ,  Sang-Hoon BAEK ,  Su-Hyeon KIM ,  Kyoung-Yun BAEK ,  Sung-Wook AHN ,  Sang-Kyu OH ,  Seung-Jae JUNG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

Abstract translation: 集成电路的制造方法，用于实施该方法的系统以及用于验证集成电路的系统可以使用包括可能违反设计规则的第一布局区域的标准单元布局。 用于设计集成电路的方法可以包括接收包括缩放增强电路布局的数据文件，以及使用设计规则和数据文件来设计第一标准单元布局。 设计第一标准单元布局可以包括使用数据文件设计第一标准单元布局的第一布局区域，以及使用设计规则设计第一标准单元布局的第二区域。

公开(公告)号：US20120220058A1

公开(公告)日：2012-08-30

申请号：US13406655

申请日：2012-02-28

Applicant: Jee-eun JUNG ,  Kyoung-yun Baek ,  Seong-woon Choi

Inventor： Jee-eun JUNG ,  Kyoung-yun Baek ,  Seong-woon Choi

IPC: H01L21/66

CPC classification number: G03F7/70125 ,  G03F1/70

Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.

Abstract translation: 一种制造半导体器件的方法包括：准备半导体器件的布局，在使用交叉极照明系统的条件下通过仿真获得布局的曝光图像的对比度，将布局分为多个子布局 曝光图像的对比度，形成具有对应于多个子布局的掩模图案的光掩模，以及在使用偶极照明系统的曝光条件下使用光掩模进行曝光处理。

公开(公告)号：US08013374B2

公开(公告)日：2011-09-06

申请号：US12465202

申请日：2009-05-13

Applicant: Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

Inventor： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

Abstract: A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

Abstract translation: 半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间 相同列的相邻有效区域。

公开(公告)号：US20090218610A1

公开(公告)日：2009-09-03

申请号：US12465234

申请日：2009-05-13

Applicant: Don-Hoon Goo ,  Han-Ku Cho ,  Joo-Tac Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

Inventor： Don-Hoon Goo ,  Han-Ku Cho ,  Joo-Tac Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

Abstract: A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns.

Abstract translation: 半导体存储器件可以包括具有多个有源区的半导体衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区域可以在第二轴线的方向上以多个列设置。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨越多个字线对，每个位线电耦合到每列的相应有源区的漏极部分，并且每个位线在不同方向上与相邻列的有源区域的漏极部分交叉 使得相同位线的不同部分在相邻列的不同有效区域上在不同方向上对准。

公开(公告)号：US20070093656A1

公开(公告)日：2007-04-26

申请号：US10582743

申请日：2003-12-29

Applicant: Seok Soo Kim ,  Jung Ho So ,  Sang Ku Lee ,  II Yong Lee ,  Myung Cho ,  kyoung Yun

Inventor： Seok Soo Kim ,  Jung Ho So ,  Sang Ku Lee ,  II Yong Lee ,  Myung Cho ,  kyoung Yun

IPC: C08B11/08

CPC classification number: C08B11/00 ,  C08B11/02 ,  C08B11/08 ,  C08B11/193

Abstract: The present invention relates to a method for preparing fine powdered cellulose ethers. In particular, the present invention relates to a method for preparing cellulose ethers in a cost-effective manner having high running efficiency of process, which comprises specifically regulating a reaction condition of each step to induce a particle refinement and significantly reduce a running load on a grinding process, in the reaction of treating finely pulverized celluloses with a caustic soda and reacting with an etherifying agent.

Abstract translation: 本发明涉及一种制备细粉状纤维素醚的方法。 特别地，本发明涉及以具有高工艺运行效率的成本有效的方式制备纤维素醚的方法，该方法包括特别地调节每个步骤的反应条件以诱导颗粒细化并显着减少在 在将精细粉碎的纤维素与苛性钠一起处理并与醚化剂反应的反应中进行。