公开(公告)号：US10546795B2

公开(公告)日：2020-01-28

申请号：US15971262

申请日：2018-05-04

Applicant: ABB Schweiz AG

Inventor： Lise Donzel ,  Juergen Schuderer ,  Jagoda Dobrzynska ,  Jan Vobecky

IPC: H01L29/06 ,  H01L23/29 ,  H01L23/31

Abstract: The present application relates to a power semiconductor device, including a substrate having a first side and a second side, the first side and the second side being located opposite to each other, wherein the first side includes a cathode and the second side includes an anode, wherein a junction termination of a p/n-junction is provided at at least one surface of the substrate, preferably at at least one of the first side and the second side, the junction termination is coated by a passivating coating, the passivating coating including at least one material selected from the group consisting of an inorganic-organic composite material, parylene, and a phenol resin comprising polymeric particles. A device as described above thus addresses issues of passivation of junction terminations and thus prevents or at least reduces the danger of fatal defects such as unstable device operation caused by changes in film properties, instability, water permeability, permeability of movable ions such as sodium, pinholes and cracks, and aluminum metal disconnection or corrosion due to degradation and stress.

公开(公告)号：US20180254233A1

公开(公告)日：2018-09-06

申请号：US15971262

申请日：2018-05-04

Applicant: ABB Schweiz AG

Inventor： Lise Donzel ,  Juergen Schuderer ,  Jagoda Dobrzynska ,  Jan Vobecky

IPC: H01L23/31 ,  H01L23/29 ,  H01L29/06

Abstract: The present application relates to a power semiconductor device, including a substrate having a first side and a second side, the first side and the second side being located opposite to each other, wherein the first side includes a cathode and the second side includes an anode, wherein a junction termination of a p/n-junction is provided at at least one surface of the substrate, preferably at at least one of the first side and the second side, the junction termination is coated by a passivating coating, the passivating coating including at least one material selected from the group consisting of an inorganic-organic composite material, parylene, and a phenol resin comprising polymeric particles. A device as described above thus addresses issues of passivation of junction terminations and thus prevents or at least reduces the danger of fatal defects such as unstable device operation caused by changes in film properties, instability, water permeability, permeability of movable ions such as sodium, pinholes and cracks, and aluminum metal disconnection or corrosion due to degradation and stress.

公开(公告)号：US20170243966A1

公开(公告)日：2017-08-24

申请号：US15421128

申请日：2017-01-31

Applicant: ABB Schweiz AG

Inventor： Marco Bellini ,  Jan Vobecky

IPC: H01L29/74 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7428 ,  H01L29/0839 ,  H01L29/66363 ,  H01L29/74

Abstract: A thyristor, in particular a phase control thyristor, is disclosed with comprises: a) a semiconductor slab, in particular a semiconductor wave or die, in which a thyristor structure is formed, b) a cathode metallization formed on a cathode region on a cathode side surface of the semiconductor slab, c) a gate metallization formed on a gate region on the cathode side surface of the semiconductor slab, d) a plurality of N discrete emitter shorts, arranged at points Pi in the cathode region, said points having point locations xi, with iε{1; . . . ; N}, e) the points Pl defining a Delaunay triangulation comprising a plurality of triangles Tj with jε{1; . . . ; M), wherein f) for a first subset of triangles Tl with lεS1⊂{1; . . . ; M), g) with each triangle Tl being characterized by a geometric quantity having values qT,l with lεS1⊂{1; . . . ; M), said geometric quantity having a mean value μ, and i) a coefficient of variation of the values qT,l with lεS1 is smaller than 0.1, preferably smaller than 0.05, and/or ii) an absolute value of a skewedness of the geometric quantities qT,l with lεS1 is smaller than 5, preferably smaller than 1, and/or iii) a Kurtosis of the geometric quantities qT,l with lεS1 is smaller than 20, preferably smaller than 10, and h) for a second subset of triangles Tm with mεS2⊂S1, for which the respective geometric quantities qT,m with mεS2 deviate from the mean value by more than a predetermined amount, in particular by more than 30%, (1) a quotient of a standard deviation of the quantities qT,m with mεS2 and a mean squared value of the geometric quantity qT,l with lεS1 is less than 1 or less than 0.1, and/or a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than

公开(公告)号：US20180108789A1

公开(公告)日：2018-04-19

申请号：US15837544

申请日：2017-12-11

Applicant: ABB Schweiz AG

Inventor： Jan Vobecky

IPC: H01L29/872 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/872 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/8083 ,  H01L29/868

Abstract: A method for manufacturing an edge termination structure for a silicon carbide power semiconductor device having a central region and an edge region is provided. The following manufacturing steps are performed: a) providing an n-doped silicon carbide substrate, b) epitaxially growing a silicon carbide n-doped drift layer on the substrate, which has a lower doping concentration than the substrate, c) creating at least one p-doped termination layer by implanting a second ion up to a maximum termination layer depth and annealing on the first main side, d) forming a doping reduction layer having a depth range, which doping reduction layer comprises at least one doping reduction region, wherein a depth of a doping concentration minimum of the doping reduction layer is greater than the maximum termination layer depth, wherein for the creation of each doping reduction region: implanting a first ion with an implantation energy in the drift layer at least in the edge region, wherein the first ion and the at least one implantation energy are chosen such that the doping reduction layer depth range is less than 10 μm, e) annealing the doping reduction layer, wherein step d) and e) are performed such that the doping concentration of the drift layer is reduced in the doping reduction layer.

公开(公告)号：US10170557B2

公开(公告)日：2019-01-01

申请号：US15826427

申请日：2017-11-29

Applicant: ABB Schweiz AG

Inventor： Marco Bellini ,  Jan Vobecky ,  Paul Commin

IPC: H01L29/10 ,  H01L29/74 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: There is provided a thyristor having emitter shorts, wherein in an orthogonal projection onto a plane parallel to a first main side, a contact area covered by an electrical contact of a first electrode layer with a first emitter layer and the emitter shorts includes areas in the shape of lanes, in which an area coverage of the emitter shorts is less than the area coverage of emitter shorts in the remaining area of the contact area, wherein the area coverage of the emitter shorts in a specific area is the area covered by the emitter shorts in that specific area relative to the specific area. The thyristor of the invention exhibits a fast turn-on process even without complicated amplifying gate structure.

公开(公告)号：US10115834B2

公开(公告)日：2018-10-30

申请号：US15837544

申请日：2017-12-11

Applicant: ABB Schweiz AG

Inventor： Jan Vobecky

IPC: H01L29/87 ,  H01L29/872 ,  H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/868

Abstract: A method for manufacturing an edge termination structure for a silicon carbide power semiconductor device having a central region and an edge region is provided. The following manufacturing steps are performed: a) providing an n-doped silicon carbide substrate, b) epitaxially growing a silicon carbide n-doped drift layer on the substrate, which has a lower doping concentration than the substrate, c) creating at least one p-doped termination layer by implanting a second ion up to a maximum termination layer depth and annealing on the first main side, d) forming a doping reduction layer having a depth range, which doping reduction layer comprises at least one doping reduction region, wherein a depth of a doping concentration minimum of the doping reduction layer is greater than the maximum termination layer depth, wherein for the creation of each doping reduction region: implanting a first ion with an implantation energy in the drift layer at least in the edge region, wherein the first ion and the at least one implantation energy are chosen such that the doping reduction layer depth range is less than 10 μm, e) annealing the doping reduction layer, wherein step d) and e) are performed such that the doping concentration of the drift layer is reduced in the doping reduction layer.

公开(公告)号：US20180040526A1

公开(公告)日：2018-02-08

申请号：US15666858

申请日：2017-08-02

Applicant: ABB Schweiz AG ,  Audi AG

Inventor： Jürgen Schuderer ,  Umamaheswara Vemulapati ,  Marco Bellini ,  Jan Vobecky

IPC: H01L23/14 ,  H01L25/18 ,  H01L23/538 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L23/147 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/535 ,  H01L23/5386 ,  H01L23/62 ,  H01L25/072 ,  H01L25/18 ,  H01L29/0634 ,  H01L29/0646 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

公开(公告)号：US10355117B2

公开(公告)日：2019-07-16

申请号：US15421128

申请日：2017-01-31

Applicant: ABB Schweiz AG

Inventor： Marco Bellini ,  Jan Vobecky

IPC: H01L29/74 ,  H01L29/08 ,  H01L29/66

Abstract: A thyristor is disclosed with a plurality of emitter shorts at points in the cathode region. The points define a Delaunay triangulation with a plurality of triangles. For a first subset of triangles a coefficient of variation of the values qT,l with l∈S1 is smaller than 0.1, and/or an absolute value of a skewedness of the geometric quantities qT,l with l∈S1 is smaller than 5, and/or a Kurtosis of the geometric quantities qT,l with l∈S1 is smaller than 20. For a second subset of triangles, a quotient of a standard deviation of the quantities qT,m with m∈S2 and a mean squared value of the geometric quantity qT,l with l∈S1 is less than 1, and/or a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than 1.0×10−2.

公开(公告)号：US20180090572A1

公开(公告)日：2018-03-29

申请号：US15826427

申请日：2017-11-29

Applicant: ABB Schweiz AG

Inventor： Marco Bellini ,  Jan Vobecky ,  Paul Commin

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/74

CPC classification number: H01L29/102 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/42308 ,  H01L29/74 ,  H01L29/7404 ,  H01L29/7428 ,  H01L29/7432

Abstract: There is provided a thyristor having emitter shorts, wherein in an orthogonal projection onto a plane parallel to a first main side, a contact area covered by an electrical contact of a first electrode layer with a first emitter layer and the emitter shorts includes areas in the shape of lanes, in which an area coverage of the emitter shorts is less than the area coverage of emitter shorts in the remaining area of the contact area, wherein the area coverage of the emitter shorts in a specific area is the area covered by the emitter shorts in that specific area relative to the specific area. The thyristor of the invention exhibits a fast turn-on process even without complicated amplifying gale structure.