公开(公告)号：US12105646B2

公开(公告)日：2024-10-01

申请号：US17539367

申请日：2021-12-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Fataneh Ghodrat

IPC: G06F13/16 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F13/1642 ,  G06T1/20 ,  G06T1/60

Abstract: A system includes a memory implementing one or more virtual queues and a processor coupled to the memory. In response to issuing one or more requests for data, a processor maps one or more of the requests for data to a return queue structure. The processor then allocates one or more virtual queues to the return queue structure based on the mapped requests. In response to allocating the virtual queues to the return queue, the processor writes the data indicated in the mapped requests to the allotted virtual queues and enables the return queue for arbitration. When the return queue is enabled for arbitration, the processor reads out the data written to the allocated virtual queues, processes the read out data, and provides the processed data to a processing pipeline.

公开(公告)号：US20210287422A1

公开(公告)日：2021-09-16

申请号：US16819014

申请日：2020-03-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Fataneh Ghodrat

IPC: G06T15/06 ,  G06T17/10 ,  G06T15/00 ,  G06T1/60 ,  G06K9/62

Abstract: Techniques for performing ray tracing for a ray are provided. The techniques include, based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident, obtaining a first portion of the bounding volume hierarchy associated with the first memory page, traversing the first portion of the bounding volume hierarchy according to a ray intersection test, based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident, and in response to the second memory page being classified as valid and non-resident, determining that a miss occurs for each node of the bounding volume hierarchy within the second memory page.

公开(公告)号：US20210065758A1

公开(公告)日：2021-03-04

申请号：US16556139

申请日：2019-08-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Fataneh Ghodrat ,  Tien E. Wei

IPC: G11C8/12 ,  G11C11/4074 ,  G06F9/38 ,  G06F12/02

Abstract: A technique for processing computer instructions is provided. The technique includes obtaining information for an instruction state memory entry for an instruction; identifying, for the instruction state memory entry, a slot in an instruction state memory having selectably powered rows and blocks, based on clustering criteria; and placing the instruction state memory entry into the identified slot.

公开(公告)号：US11996166B2

公开(公告)日：2024-05-28

申请号：US16556139

申请日：2019-08-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Fataneh Ghodrat ,  Tien E. Wei

IPC: G06F12/00 ,  G06F9/38 ,  G06F12/02 ,  G11C8/12 ,  G11C11/4074

CPC classification number: G11C8/12 ,  G06F9/3804 ,  G06F12/0246 ,  G11C11/4074 ,  G06F2212/1028

Abstract: A technique for processing computer instructions is provided. The technique includes obtaining information for an instruction state memory entry for an instruction; identifying, for the instruction state memory entry, a slot in an instruction state memory having selectably powered rows and blocks, based on clustering criteria; and placing the instruction state memory entry into the identified slot.

公开(公告)号：US11720499B2

公开(公告)日：2023-08-08

申请号：US17134790

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Fataneh Ghodrat ,  Stephen W. Somogyi ,  Zhenhong Liu

IPC: G06F12/0891 ,  G06T1/60 ,  G06T1/20 ,  G06F12/0831

CPC classification number: G06F12/0891 ,  G06F12/0833 ,  G06T1/20 ,  G06T1/60

Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.

公开(公告)号：US10198789B2

公开(公告)日：2019-02-05

申请号：US15377998

申请日：2016-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel Schneider ,  Fataneh Ghodrat

IPC: G06T1/60 ,  G06F12/0815 ,  G06F12/0877 ,  G06F15/80 ,  G06T15/00 ,  G06T1/20

Abstract: Techniques for allowing cache access returns out of order are disclosed. A return ordering queue exists for each of several cache access types and stores outstanding cache accesses in the order in which those accesses were made. When a cache access request for a particular type is at the head of the return ordering queue for that type and the cache access is available for return to the wavefront that made that access, the cache system returns the cache access to the wavefront. Thus, cache accesses can be returned out of order with respect to cache accesses of different types. Allowing out-of-order returns can help to improve latency, for example in the situation where a relatively low-latency access type (e.g., a read) is issued after a relatively high-latency access type (e.g., a texture sampler operation).

公开(公告)号：US20180165790A1

公开(公告)日：2018-06-14

申请号：US15377998

申请日：2016-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel Schneider ,  Fataneh Ghodrat

IPC: G06T1/60 ,  G06F12/0877 ,  G06F12/0815 ,  G06F15/80

CPC classification number: G06T1/60 ,  G06F12/0815 ,  G06F12/0877 ,  G06F15/8007 ,  G06F2212/455 ,  G06F2212/60 ,  G06F2212/621 ,  G06T1/20 ,  G06T15/005

Abstract: Techniques for allowing cache access returns out of order are disclosed. A return ordering queue exists for each of several cache access types and stores outstanding cache accesses in the order in which those accesses were made. When a cache access request for a particular type is at the head of the return ordering queue for that type and the cache access is available for return to the wavefront that made that access, the cache system returns the cache access to the wavefront. Thus, cache accesses can be returned out of order with respect to cache accesses of different types. Allowing out-of-order returns can help to improve latency, for example in the situation where a relatively low-latency access type (e.g., a read) is issued after a relatively high-latency access type (e.g., a texture sampler operation).