公开(公告)号：US10715139B2

公开(公告)日：2020-07-14

申请号：US16120836

申请日：2018-09-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Mangalore Anand ,  Jagadeesh Anathahalli Singrigowda ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K19/003 ,  H03K17/687

Abstract: Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.

公开(公告)号：US11418189B2

公开(公告)日：2022-08-16

申请号：US17081540

申请日：2020-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadeesh Anathahalli Singrigowda ,  Ashish Sahu ,  Rajesh Mangalore Anand ,  Aniket Bharat Waghide ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K19/0948 ,  H03K17/687 ,  H03K19/0185 ,  G05F3/20 ,  H03K19/003 ,  H03K17/0812 ,  G01R19/165

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

公开(公告)号：US20230095805A1

公开(公告)日：2023-03-30

申请号：US17487569

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rajesh Mangalore Anand ,  Prasant Kumar Vallur ,  Piyush Gupta ,  Girish Anathahalli Singrigowda ,  Jagadeesh Anathahalli Singrigowda

IPC: H03K19/17788 ,  H03K19/003 ,  H03K19/0185

Abstract: Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.

公开(公告)号：US20210409020A1

公开(公告)日：2021-12-30

申请号：US17081540

申请日：2020-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadeesh Anathahalli Singrigowda ,  Ashish Sahu ,  Rajesh Mangalore Anand ,  Aniket Bharat Waghide ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K17/687 ,  H03K19/0948 ,  H03K19/0185 ,  H03K19/003 ,  H03K17/0812 ,  G01R19/165 ,  G05F3/20

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

公开(公告)号：US20200076429A1

公开(公告)日：2020-03-05

申请号：US16120836

申请日：2018-09-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Mangalore Anand ,  Jagadeesh Anathahalli Singrigowda ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K17/687 ,  H03K19/003

Abstract: Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.

公开(公告)号：US20240210449A1

公开(公告)日：2024-06-27

申请号：US18089057

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Thanapandi Ganesan ,  Prateek Mishra ,  Pramod Baliga Kokkada ,  Rajesh Mangalore Anand ,  Aniket Bharat Waghide ,  Animesh Jain ,  Girish Anathahally Singrigowda ,  Dhruvin Devangbhai Shah

IPC: G01R19/165

CPC classification number: G01R19/16528

Abstract: A power sensing circuit in a first voltage domain senses an input voltage from a second voltage domain and provides a power OK signal. The maximum supply voltage of the first voltage domain is above a maximum tolerance for devices in the first voltage domain. Accordingly, protection techniques are employed to ensure that the potential difference between any two terminals of devices in the power sensing circuit does not exceed the maximum tolerance limit. The protection techniques utilize reference voltage-based techniques including level shifting and use of protection devices in transistor stacks. An over-voltage tolerant Schmitt trigger circuit is also employed in the power sensing circuit. A trip point device on the input of the power sensing circuit utilizes a programmable bias voltage to adjust the trip point of the power sensing circuit to accommodate different maximum input voltages from the second voltage domain.

公开(公告)号：US11764789B2

公开(公告)日：2023-09-19

申请号：US17487569

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rajesh Mangalore Anand ,  Prasant Kumar Vallur ,  Piyush Gupta ,  Girish Anathahalli Singrigowda ,  Jagadeesh Anathahalli Singrigowda

IPC: H03K19/17788 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K19/17788 ,  H03K19/00315 ,  H03K19/00384 ,  H03K19/018507

Abstract: Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.