中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

59 records (took 0.02 seconds)

    METHOD FOR MANUFACTURING A PACKAGE STRUCTURE
    1.
    发明公开
    METHOD FOR MANUFACTURING A PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20240088091A1

    公开(公告)日：2024-03-14

    申请号：US17940827

    申请日：2022-09-08

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

    IPC: H01L23/00

    CPC classification number: H01L24/97 ,  H01L2224/95136

    Abstract: A method for manufacturing a package structure includes: providing a first electrical element and a second electrical element on a surface of a first carrier, wherein the second electrical element is shifted with respect to the first electrical element; and moving the first electrical element along at least one direction substantially parallel with the surface of the first carrier until a first surface of the first electrical element is substantially aligned with a first surface of the second electrical element from a top view.

    SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20210035908A1

    公开(公告)日：2021-02-04

    申请号：US16528352

    申请日：2019-07-31

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chih-Cheng LEE ,  Kuang Hsiung CHEN

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

    Abstract: A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.

    SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS
    3.
    发明申请
    SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS 审中-公开

    公开(公告)号：US20190287867A1

    公开(公告)日：2019-09-19

    申请号：US16297451

    申请日：2019-03-08

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed adjacent to the first dielectric structure of the wiring structure, and defines at least one through hole corresponding to the exposed pad portion of the first circuit layer.

    REDUCED-DIMENSION VIA-LAND STRUCTURE AND METHOD OF MAKING THE SAME
    5.
    发明申请
    REDUCED-DIMENSION VIA-LAND STRUCTURE AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20170231093A1

    公开(公告)日：2017-08-10

    申请号：US15019776

    申请日：2016-02-09

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Po-Shu PENG

    IPC: H05K1/11 ,  H05K3/10 ,  H05K3/40

    CPC classification number: H05K1/116 ,  H05K3/0035 ,  H05K3/10 ,  H05K3/4038

    Abstract: A package substrate includes a dielectric layer, a conductive via disposed in the dielectric layer, and a conductive pattern layer exposed from a first surface of the dielectric layer. The conductive pattern layer includes traces and a via land, the via land extends into the conductive via, and a circumferential portion of the via land is encompassed by the conductive via. A method of making a package substrate includes forming a conductive pattern layer including traces and a via land, providing a dielectric layer to cover the conductive pattern layer, and forming a via hole. Forming the via hole is performed by removing a portion of the dielectric layer and exposing a bottom surface of the via land and at least a portion of a side surface of the via land. A conductive material is applied into the via hole to form a conductive via covering the via land.

    CIRCUIT BOARD WITH EMBEDDED PASSIVE COMPONENT AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    CIRCUIT BOARD WITH EMBEDDED PASSIVE COMPONENT AND MANUFACTURING METHOD THEREOF 有权
    具有嵌入式被动元件的电路板及其制造方法

    公开(公告)号：US20160150651A1

    公开(公告)日：2016-05-26

    申请号：US14550615

    申请日：2014-11-21

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

    IPC: H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H01L21/48 ,  H01L23/498

    CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/007 ,  H05K3/34 ,  H05K2203/06 ,  H01L2924/00

    Abstract: The present disclosure relates to a semiconductor device substrate and a method for making the same. The semiconductor device substrate includes a first dielectric layer, a second dielectric layer and an electronic component. The first dielectric layer includes a body portion, and a wall portion protruded from a first surface of the body portion. The wall portion has an end. The second dielectric layer has a first surface and an opposing second surface. The first surface of the second dielectric layer is adjacent to the first surface of the body portion. The second dielectric layer surrounds the wall portion. The end of the wall portion extends beyond the second surface of the second dielectric layer. The electronic component includes a first electrical contact and a second electrical contact. At least a part of the electronic component is surrounded by the wall portion.

    Abstract translation: 本公开涉及一种半导体器件基板及其制造方法。 半导体器件基板包括第一介电层，第二介电层和电子部件。 第一电介质层包括主体部分和从主体部分的第一表面突出的壁部分。 壁部分有一端。 第二电介质层具有第一表面和相对的第二表面。 第二电介质层的第一表面与主体部分的第一表面相邻。 第二电介质层围绕壁部。 壁部分的端部延伸超过第二介电层的第二表面。 电子部件包括第一电接触和第二电接触。 电子部件的至少一部分被壁部包围。

    SEMICONDUCTOR DEVICE PACKAGES AND METHOD FOR MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE PACKAGES AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20210090931A1

    公开(公告)日：2021-03-25

    申请号：US16578062

    申请日：2019-09-20

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

    IPC: H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

    Abstract: A semiconductor device package includes a carrier, a patterned passivation layer and a first patterned conductive layer. The patterned passivation layer is disposed on the carrier. The first patterned conductive layer is disposed on the carrier and surrounded by the patterned passivation layer. The first patterned conductive layer has a first portion and a second portion electrically disconnected from the first portion. The first portion has a first surface adjacent to the carrier and exposed by the patterned passivation layer. The second portion has a first surface adjacent to the carrier exposed by the patterned passivation layer. The first surface of the first portion is in direct contact with an insulation medium.

Patent Agency Ranking