公开(公告)号：US20230061843A1

公开(公告)日：2023-03-02

申请号：US17460053

申请日：2021-08-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L23/31

Abstract: An electronic package is provided. The electronic package includes a first circuit structure, a second circuit structure, and an underfill. The second circuit structure is disposed over the first circuit structure. The underfill is disposed between the first circuit structure and the second circuit structure. An inner portion of the underfill has an inner lateral surface adjacent to and is substantially conformal with a lateral surface of the second circuit structure. A first top end of the inner lateral surface is not level with a top surface of the second circuit structure. An outer portion of the underfill has a second top end higher than the first top end.

公开(公告)号：US20240088091A1

公开(公告)日：2024-03-14

申请号：US17940827

申请日：2022-09-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L23/00

CPC classification number: H01L24/97 ,  H01L2224/95136

Abstract: A method for manufacturing a package structure includes: providing a first electrical element and a second electrical element on a surface of a first carrier, wherein the second electrical element is shifted with respect to the first electrical element; and moving the first electrical element along at least one direction substantially parallel with the surface of the first carrier until a first surface of the first electrical element is substantially aligned with a first surface of the second electrical element from a top view.

公开(公告)号：US20210384148A1

公开(公告)日：2021-12-09

申请号：US16895989

申请日：2020-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuanhao YU ,  Cheng-Lin HO ,  Yu-Lin SHIH ,  Shih-Chun LI

IPC: H01L23/66 ,  H01Q1/22

Abstract: A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.

公开(公告)号：US20210090931A1

公开(公告)日：2021-03-25

申请号：US16578062

申请日：2019-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A semiconductor device package includes a carrier, a patterned passivation layer and a first patterned conductive layer. The patterned passivation layer is disposed on the carrier. The first patterned conductive layer is disposed on the carrier and surrounded by the patterned passivation layer. The first patterned conductive layer has a first portion and a second portion electrically disconnected from the first portion. The first portion has a first surface adjacent to the carrier and exposed by the patterned passivation layer. The second portion has a first surface adjacent to the carrier exposed by the patterned passivation layer. The first surface of the first portion is in direct contact with an insulation medium.

公开(公告)号：US20200350223A1

公开(公告)日：2020-11-05

申请号：US16402127

申请日：2019-05-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih Cheng LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device package includes a dielectric layer, a package body and a protection structure. The dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The package body is disposed on the first surface of the dielectric layer. The package body covers a first portion of the lateral surface of the dielectric layer and exposes a second portion of the lateral surface of the dielectric layer. The protection structure is disposed on the second portion of the lateral surface of the dielectric layer.

公开(公告)号：US20190035753A1

公开(公告)日：2019-01-31

申请号：US15665289

申请日：2017-07-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A substrate structure includes a dielectric layer, a first circuit layer, at least one conductive structure and a first protective layer. The first circuit layer is disposed adjacent to a first surface of the dielectric layer. The conductive structure includes a first portion and a second portion. The first portion is disposed on the first circuit layer. The first protective layer is disposed on the dielectric layer and contacts at least a portion of a sidewall of the first portion of the conductive structure. The first circuit layer and the conductive structure are integrally formed.

公开(公告)号：US20160133562A1

公开(公告)日：2016-05-12

申请号：US14703794

申请日：2015-05-04

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chih-Cheng LEE ,  Yuan-Chang SU ,  Yu-Lin SHIH ,  You-Lung Yen

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L21/481 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/92144

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.

Abstract translation: 本公开涉及一种半导体封装及其制造方法。 半导体封装包括封装层，封装层内的部件，第一介电层，第二介电层，第一图案化导电层和第二图案化导电层。 该部件包括在该部件的前表面上的焊盘。 第一介电层设置在封装层的表面上。 第二电介质层设置在第一电介质层的表面上。 第一和第二电介质层限定了从第二电介质层延伸到各个焊盘的通孔。 第一图案化导电层设置在第一介电层内并包围通孔。 第二图案化导电层设置在第二介电层内并包围通孔。

公开(公告)号：US20220115339A1

公开(公告)日：2022-04-14

申请号：US17067561

申请日：2020-10-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/49 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/40

Abstract: An antenna package includes a conductive layer, an interconnection structure and an antenna. The interconnection structure is disposed on the conductive layer. The interconnection structure includes a conductive via and a first package body. The conductive via has a first surface facing the conductive layer, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The first package body covers the lateral surface of the conductive via and exposes the first surface and the second surface of the conductive via. The first package body is spaced apart from the conductive layer. The antenna is electrically connected to the second surface of the conductive via.

公开(公告)号：US20210202412A1

公开(公告)日：2021-07-01

申请号：US16730390

申请日：2019-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit structure. The circuit structure includes a dielectric layer and a bonding pad. The dielectric layer has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface, where the dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall. The bonding pad is disposed in the recess, where a first pad surface of the bonding pad is adjacent to the first dielectric surface, a second pad surface of the bonding pad is adjacent to the second dielectric surface, and an edge of the bonding pad is spaced from the sidewall of the recess by a first distance.

公开(公告)号：US20190164782A1

公开(公告)日：2019-05-30

申请号：US15824919

申请日：2017-11-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih Cheng LEE

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/11622 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81192 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/013 ,  H01L2924/00014

Abstract: A semiconductor substrate includes a dielectric layer, a first patterned conductive layer and a first connection element. The dielectric layer has a first surface. The first patterned conductive layer has a first surface and is disposed adjacent to the first surface of the dielectric layer. The first connection element is disposed on the first surface of the first patterned conductive layer. The first connection element includes a first portion, a second portion and a seed layer disposed between the first portion and the second portion. The first portion of the first connection element and the first patterned conductive layer are formed to be a monolithic structure.