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公开(公告)号：US20190158087A1
公开(公告)日：2019-05-23
申请号：US16166858
申请日：2018-10-22
Applicant: Analog Devices, Inc.
Inventor： Junhua Shen
IPC: H03K17/687 , H03M1/12
Abstract: A sampling circuit comprises a switch circuit and a gate bootstrapping circuit. The switch circuit includes a switch input to receive an input voltage, a gate input, and a switch output. The gate bootstrapping circuit provides a boosted clock signal to the gate input of the switch circuit. The boosted voltage of the boosted clock signal tracks the input voltage by a voltage offset. The gate bootstrapping circuit includes a single boost capacitance coupled between a first circuit node and a second circuit node. A high supply voltage is applied to the first circuit node and the input voltage is applied the second circuit node to generate the boosted voltage on the single boost capacitance.
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公开(公告)号：US11150280B2
公开(公告)日：2021-10-19
申请号：US16285046
申请日：2019-02-25
Applicant: Analog Devices, Inc.
Inventor： Junhua Shen
Abstract: A current measurement circuit may use a probabilistic technique to determine a current from a circuit block. In one embodiment, the circuit includes a comparator circuit, a first current sensing element (such as a first resistor), and a control circuit. The first current sensing element is coupled to the comparator circuit to establish a first comparator input signal representative of the current at an input of the comparator circuit. The control circuit is coupled to the comparator circuit to obtain a first plurality of comparator output decisions corresponding to the first current sensing element for a specified count, determine a first proportion of comparator output decisions meeting a specified criterion, and determine a voltage value of the first comparator input signal from the first proportion. The control circuit is configured to determine a current value using the voltage value of the first comparator input signal and an impedance value of the first current sensing element. The current measurement circuit is relatively low-cost and easy to implement, without requiring a precision reference voltage, current, and/or high-cost analog-to-digital converters (ADCs).
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公开(公告)号：US10454492B1
公开(公告)日：2019-10-22
申请号：US16012576
申请日：2018-06-19
Applicant: Analog Devices, inc.
Inventor： Akira Shikata , Junhua Shen , Anping Liu
Abstract: A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.
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公开(公告)号：US09667266B1
公开(公告)日：2017-05-30
申请号：US15048526
申请日：2016-02-19
Applicant: Analog Devices, Inc.
Inventor： Junhua Shen , Michael C. W. Coln
CPC classification number: H03M1/1245 , G11C27/026 , H03M1/145 , H03M1/468
Abstract: A voltage sampling circuit is provided that may directly connect a non-zero power supply voltage VDD to switching circuits during input voltage sampling, setting a common mode voltage without using reference voltages produced by a reference voltage generator circuit, and without requiring a common mode buffer circuit. The voltage sampling circuit may be used in an operational amplifier input stage such as for a pipelined ADC circuit, or in a comparator circuit. A SAR ADC circuit is also provided, comprising a control circuit, the voltage sampling circuit, a capacitor array, and a comparator circuit for comparing outputs occurring from charge redistributions. The voltage sampling circuit may enable increased power efficiency, avoid leakage concerns, and increase maximum input voltage swing. Reference plate switches in the voltage sampling circuit may include gate-boosted devices or thicker-oxide I/O devices. The devices may include n-channel field-effect transistors or high threshold voltage p-channel field-effect transistors.
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公开(公告)号：US09571114B1
公开(公告)日：2017-02-14
申请号：US15019430
申请日：2016-02-09
Applicant: Analog Devices, Inc.
Inventor： Junhua Shen , Edward C. Guthrie
CPC classification number: H03M1/0612 , H03M1/069 , H03M1/1245 , H03M1/46
Abstract: An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits.
Abstract translation: 模数转换器（ADC）电路包括至少包括N + n个加权电路组件的数模（DAC）电路，其中N和n是大于零的正整数，n是重复数 ADC电路的最低有效位（LSB）的位; 采样电路，被配置为在所述ADC电路的输入处对输入电压进行采样，并将采样的电压施加到所述加权电路部件; 比较器电路，被配置为在比特试验期间将DAC的输出电压与指定的阈值电压进行比较; 以及逻辑电路，被配置为对所述至少N + n个加权电路组件执行比特测试，并根据n个LSB重复比特的值调整一个或多个N比特试验中的一个或多个参数。
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Patent Agency Ranking
公开(公告)号：US11876346B2
公开(公告)日：2024-01-16
申请号：US16453706
申请日：2019-06-26
Applicant: Analog Devices, Inc.
Inventor： Junhua Shen
CPC classification number: H01S5/0428 , G01S7/484 , G01S17/10
Abstract: A laser pulse emitter circuit comprises a laser diode and a laser diode driver circuit. The laser diode driver circuit includes an inductive circuit element in series with the laser diode, at least one capacitive circuit element connected in series with the inductive circuit element, and a switch circuit configured to activate the laser diode using duty cycling that includes an on-period and an off-period, wherein energy used in an activation of the laser diode is stored in the inductive circuit element and the at least one capacitive circuit element, and the stored energy is recycled by use in a subsequent activation of the laser diode.
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公开(公告)号：US20200271701A1
公开(公告)日：2020-08-27
申请号：US16285046
申请日：2019-02-25
Applicant: Analog Devices, Inc.
Inventor： Junhua Shen
Abstract: A current measurement circuit may use a probabilistic technique to determine a current from a circuit block. In one embodiment, the circuit includes a comparator circuit, a first current sensing element (such as a first resistor), and a control circuit. The first current sensing element is coupled to the comparator circuit to establish a first comparator input signal representative of the current at an input of the comparator circuit. The control circuit is coupled to the comparator circuit to obtain a first plurality of comparator output decisions corresponding to the first current sensing element for a specified count, determine a first proportion of comparator output decisions meeting a specified criterion, and determine a voltage value of the first comparator input signal from the first proportion. The control circuit is configured to determine a current value using the voltage value of the first comparator input signal and an impedance value of the first current sensing element. The current measurement circuit is relatively low-cost and easy to implement, without requiring a precision reference voltage, current, and/or high-cost analog-to-digital converters (ADCs).
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公开(公告)号：US10205462B2
公开(公告)日：2019-02-12
申请号：US14949423
申请日：2015-11-23
Applicant: ANALOG DEVICES, INC.
Inventor： Junhua Shen , Mark D. Maddox , Ronald Alan Kapusta
Abstract: A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).
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公开(公告)号：US09608655B1
公开(公告)日：2017-03-28
申请号：US15170051
申请日：2016-06-01
Applicant: Analog Devices, Inc.
Inventor： Hongxing Li , Junhua Shen , Michael Mueck , Michael C. W. Coln
CPC classification number: H03M1/1009 , H03M1/0639 , H03M1/066 , H03M1/069 , H03M1/124 , H03M1/145 , H03M1/164 , H03M1/466
Abstract: An analog-to-digital converter (ADC) system can sample an input voltage for at least a first conversion into a first N1-bit digital value and to use the same input voltage sample for at least a second conversion into a second N2-bit digital value. A difference between a result of the first conversion and a result of the second conversion can be driven toward zero to adjust weights of one or more of the bits to calibrated values for use in one or more subsequent analog-to-digital conversions of subsequent samples of the input voltage. Shuffling, dithering, or the like can help ensure that at least a portion of the decision paths used in the second conversion are different from the decision paths used in the first conversion. Calibration can be performed in the background while the the ADC is converting in a normal mode of operation.
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公开(公告)号：US10547308B2
公开(公告)日：2020-01-28
申请号：US16166858
申请日：2018-10-22
Applicant: Analog Devices, Inc.
Inventor： Junhua Shen
IPC: H03M1/12 , H03K17/687 , H03M1/00
Abstract: A sampling circuit comprises a switch circuit and a gate bootstrapping circuit. The switch circuit includes a switch input to receive an input voltage, a gate input, and a switch output. The gate bootstrapping circuit provides a boosted clock signal to the gate input of the switch circuit. The boosted voltage of the boosted clock signal tracks the input voltage by a voltage offset. The gate bootstrapping circuit includes a single boost capacitance coupled between a first circuit node and a second circuit node. A high supply voltage is applied to the first circuit node and the input voltage is applied the second circuit node to generate the boosted voltage on the single boost capacitance.
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