公开(公告)号：US20190148229A1

公开(公告)日：2019-05-16

申请号：US15810836

申请日：2017-11-13

Applicant: Analog Devices Global Unlimited Company

Inventor： Jan Kubik ,  Bernard P. Stenson ,  Michael Noel Morrissey

IPC: H01L21/768 ,  H01L49/02 ,  H01L21/288 ,  H01L21/033 ,  H01L23/522

Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

公开(公告)号：US20180061569A1

公开(公告)日：2018-03-01

申请号：US15248775

申请日：2016-08-26

Applicant: Analog Devices Global

Inventor： Jan Kubík ,  Bernard Patrick Stenson ,  Shane Patrick Geary ,  Michael Noel Morrissey

IPC: H01F41/04 ,  H01F41/02 ,  H01F27/28 ,  H01F1/03

CPC classification number: H01F41/041 ,  H01F1/0315 ,  H01F27/2804 ,  H01F41/0206 ,  H01F41/046 ,  H01F2027/2809 ,  H01F2027/2819

Abstract: The disclosure relates to the manufacture of inductive components, in particular transformers, using a combination of microfabrication techniques and discrete component placement. By using a prefabricated core, the core may be made much thicker than one that is deposited using microfabrication techniques. As such, saturation occurs later and the efficiency of the transformer is improved. This is done at a much lower cost than the cost of producing a thicker core by depositing multiple layers using microfabrication techniques.

公开(公告)号：US20200328114A1

公开(公告)日：2020-10-15

申请号：US16914900

申请日：2020-06-29

Applicant: Analog Devices Global Unlimited Company

Inventor： Jan Kubik ,  Bernard P. Stenson ,  Michael Noel Morrissey

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/522 ,  H01L21/288 ,  H01L21/033 ,  C23C18/16 ,  H01L23/532 ,  C25D5/02 ,  C25D7/12 ,  C25D5/10 ,  H05K3/24 ,  H05K3/18 ,  H05K3/42

Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

公开(公告)号：US10699948B2

公开(公告)日：2020-06-30

申请号：US15810836

申请日：2017-11-13

Applicant: Analog Devices Global Unlimited Company

Inventor： Jan Kubik ,  Bernard P. Stenson ,  Michael Noel Morrissey

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/288 ,  H01L21/033 ,  C23C18/16 ,  H01L23/532 ,  H01L49/02 ,  C25D5/02 ,  C25D7/12 ,  C25D5/10 ,  H05K3/24 ,  H05K3/18 ,  H05K3/42 ,  H05K1/02

Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

公开(公告)号：US09887687B2

公开(公告)日：2018-02-06

申请号：US14608072

申请日：2015-01-28

Applicant: Analog Devices Global

Inventor： Seamus Paul Whiston ,  Bernard Patrick Stenson ,  Michael Noel Morrissey ,  Michael John Flynn

IPC: H05K3/30 ,  H05K1/18 ,  H03H9/17 ,  H03H9/46 ,  H03H9/22 ,  H03H9/15 ,  H03H9/24 ,  H03H9/02

CPC classification number: H03H9/462 ,  H01L2224/48227 ,  H03H9/174 ,  H03H9/22 ,  H03H2009/02165 ,  H03H2009/155 ,  H03H2009/2421

Abstract: A method of trimming a component is provided in which the component is protected from oxidation or changes in stress after trimming. As part of the method, a protective glass cover is bonded to the surface of a semiconductor substrate prior to trimming (e.g., laser trimming) of a component. This can protect the component from oxidation after trimming, which may change its value or a parameter of the component. It can also protect the component from changes in stress acting on it or on the die adjacent it during packaging, which may also change a value or parameter of the component.

公开(公告)号：US09484136B2

公开(公告)日：2016-11-01

申请号：US13927459

申请日：2013-06-26

Applicant: ANALOG DEVICES GLOBAL

Inventor： Michael Noel Morrissey ,  Jan Kubik ,  Shane Patrick Geary ,  Patrick Martin McGuinness ,  Catriona Marie O'Sullivan

IPC: H01F5/00 ,  H01F27/28 ,  H01F3/00 ,  H01L43/02 ,  H01L43/12 ,  H01F27/24 ,  H01F27/245

CPC classification number: H01F3/00 ,  H01F27/24 ,  H01F27/245 ,  H01F27/2804 ,  H01F2027/2809 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetic core is provided for an integrated circuit, the magnetic core comprising: a plurality of layers of magnetically functional material; a plurality of layers of a first insulating material; and at least one layer of an secondary insulating material; wherein layers of the first insulating material are interposed between layers of the magnetically functional material to form subsections of the magnetic core, and the at least one layer of second insulating material is interposed between adjacent subsections.

Abstract translation: 为集成电路提供磁芯，该磁芯包括：多层磁性功能材料; 多层第一绝缘材料; 和至少一层次级绝缘材料; 其中所述第一绝缘材料的层插入在所述磁性功能材料的层之间以形成所述磁芯的子部分，并且所述至少一层第二绝缘材料插入在相邻的子部分之间。

公开(公告)号：US20160219719A1

公开(公告)日：2016-07-28

申请号：US14608072

申请日：2015-01-28

Applicant: Analog Devices Global

Inventor： Seamus Paul Whiston ,  Bernard Patrick Stenson ,  Michael Noel Morrissey ,  Michael John Flynn

IPC: H05K3/30 ,  H03H9/22 ,  H05K1/02 ,  H03H9/54 ,  H03H9/62 ,  H05K1/18 ,  H03H9/17 ,  H03H9/46

CPC classification number: H03H9/462 ,  H01L2224/48227 ,  H03H9/174 ,  H03H9/22 ,  H03H2009/02165 ,  H03H2009/155 ,  H03H2009/2421

Abstract: A method of trimming a component is provided in which the component is protected from oxidation or changes in stress after trimming. As part of the method, a protective glass cover is bonded to the surface of a semiconductor substrate prior to trimming (e.g., laser trimming) of a component. This can protect the component from oxidation after trimming, which may change its value or a parameter of the component. It can also protect the component from changes in stress acting on it or on the die adjacent it during packaging, which may also change a value or parameter of the component.

Abstract translation: 提供一种修整组分的方法，其中保护组分免受氧化或修剪后的应力变化。 作为该方法的一部分，在组件的修整（例如，激光修整）之前，将保护性玻璃盖结合到半导体衬底的表面。 这可以保护组件在修剪后免受氧化，这可能会改变其组件的值或参数。 它还可以保护组件免受包装过程中作用在其上或与模具相邻的模具上的应力变化，这也可能改变组件的值或参数。