公开(公告)号：US20150070200A1

公开(公告)日：2015-03-12

申请号：US14537532

申请日：2014-11-10

Applicant: ANALOG DEVICES GLOBAL

Inventor： Zhao Li ,  SHIPRA BHAL ,  KEVIN GLENN GARD ,  DAVID NELSON ALLDRED ,  CHRISTOPHER MAYER ,  TREVOR CLIFFORD CALDWELL ,  DAVID J. McLAURIN ,  VICTOR KOZLOV

IPC: H03M3/00 ,  H03M1/10

CPC classification number: H03M3/384 ,  H03M1/00 ,  H03M1/1009 ,  H03M1/12 ,  H03M3/458

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。

公开(公告)号：US20160373101A1

公开(公告)日：2016-12-22

申请号：US15182430

申请日：2016-06-14

Applicant: ANALOG DEVICES GLOBAL

Inventor： Yunzhi Dong ,  VICTOR KOZLOV ,  WENHUA W. YANG ,  TREVOR CLIFFORD CALDWELL ,  HAJIME SHIBATA

IPC: H03K5/14 ,  H03M3/00 ,  H03H7/30 ,  H03M1/00

CPC classification number: H03K5/14 ,  H03H7/30 ,  H03K2005/00254 ,  H03K2005/00267 ,  H03M1/001 ,  H03M1/164 ,  H03M3/464

Abstract: An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.

Abstract translation: 在连续时间（CT）模数转换器（ADC）中使用的集成恒定时间延迟电路可以用RC晶格结构来实现，以提供例如无源全通晶格滤波器。 在一些实施例中，可以使用由去耦电容产生的附加极点来提供低通滤波效应。 电阻器 - 电容器“RC”晶格结构可以是恒定电阻电感器“LC”晶格实现的替代。 ADC架构由于RC实现而受益，因为其易于阻抗缩放和面积更小。

公开(公告)号：US20170179971A1

公开(公告)日：2017-06-22

申请号：US15282586

申请日：2016-09-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： ZHAO LI ,  HAJIME SHIBATA ,  TREVOR CLIFFORD CALDWELL ,  RICHARD E. SCHREIER ,  VICTOR KOZLOV ,  DAVID NELSON ALLDRED ,  PRAWAL MAN SHRESTHA

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/36

CPC classification number: H03M1/1023 ,  H03M1/1004 ,  H03M1/1038 ,  H03M1/1085 ,  H03M1/361 ,  H03M3/378 ,  H03M3/384

Abstract: A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.