公开(公告)号：US20170179971A1

公开(公告)日：2017-06-22

申请号：US15282586

申请日：2016-09-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： ZHAO LI ,  HAJIME SHIBATA ,  TREVOR CLIFFORD CALDWELL ,  RICHARD E. SCHREIER ,  VICTOR KOZLOV ,  DAVID NELSON ALLDRED ,  PRAWAL MAN SHRESTHA

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/36

CPC classification number: H03M1/1023 ,  H03M1/1004 ,  H03M1/1038 ,  H03M1/1085 ,  H03M1/361 ,  H03M3/378 ,  H03M3/384

Abstract: A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

公开(公告)号：US20160373101A1

公开(公告)日：2016-12-22

申请号：US15182430

申请日：2016-06-14

Applicant: ANALOG DEVICES GLOBAL

Inventor： Yunzhi Dong ,  VICTOR KOZLOV ,  WENHUA W. YANG ,  TREVOR CLIFFORD CALDWELL ,  HAJIME SHIBATA

IPC: H03K5/14 ,  H03M3/00 ,  H03H7/30 ,  H03M1/00

CPC classification number: H03K5/14 ,  H03H7/30 ,  H03K2005/00254 ,  H03K2005/00267 ,  H03M1/001 ,  H03M1/164 ,  H03M3/464

Abstract: An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.

Abstract translation: 在连续时间（CT）模数转换器（ADC）中使用的集成恒定时间延迟电路可以用RC晶格结构来实现，以提供例如无源全通晶格滤波器。 在一些实施例中，可以使用由去耦电容产生的附加极点来提供低通滤波效应。 电阻器 - 电容器“RC”晶格结构可以是恒定电阻电感器“LC”晶格实现的替代。 ADC架构由于RC实现而受益，因为其易于阻抗缩放和面积更小。

公开(公告)号：US20160359498A1

公开(公告)日：2016-12-08

申请号：US15240278

申请日：2016-08-18

Applicant: ANALOG DEVICES GLOBAL

Inventor： HAJIME SHIBATA

IPC: H03M1/44 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/44 ,  H03M1/001 ,  H03M1/002 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/167

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract translation: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号，并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器，产生重构信号的解码器，产生延迟信号的延迟转换器和产生残差信号的放大器，其中延迟信号可以是连续电流信号。