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公开(公告)号：US20230305924A1
公开(公告)日：2023-09-28
申请号：US17804950
申请日：2022-06-01
Applicant: Apple Inc.
Inventor： Farid Nemati , Steven R. Hutsell , Derek R. Kumar , Bernard J. Semeria , James Vash , Era K. Nangia , Gregory S. Mathews
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/106 , G06F11/0772
Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.
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公开(公告)号：US20190079799A1
公开(公告)日：2019-03-14
申请号：US15853239
申请日：2017-12-22
Applicant: Apple Inc.
Inventor： Derek R. Kumar , Thomas Brogan Duffy, JR.
Abstract: Systems, apparatuses, and methods for efficiently selecting compressors for data compression are described. In various embodiments, a computing system includes at least one processor and multiple codecs such as one or more hardware codecs and one or more software codecs executable by the processor. The computing system receives a workload and processes instructions, commands and routines corresponding to the workload. One or more of the tasks in the workload are data compression tasks. Current condition(s) are determined during the processing of the workload by the computing system. Conditions are determined to be satisfied based on comparing current selected characteristics to respective thresholds. In one example, when the compressor selector determines a difference between a target compression ratio and an expected compression ratio of the first codec exceeds a threshold, the compressor selector switches from hardware codecs to software codecs.
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公开(公告)号：US10203746B2
公开(公告)日：2019-02-12
申请号：US14503318
申请日：2014-09-30
Applicant: Apple Inc.
Inventor： Derek R. Kumar
Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device monitors the thermal profile of the device, where the device executes a plurality of tasks that utilizes a central processing unit of the device. In addition, the plurality of tasks includes a high QoS task and a low QoS process. If the thermal profile of the device exceeds a thermal threshold, the device increases a first CPU throttling for the low QoS task and maintains a second CPU throttling for the high QoS task. The device further executes the low QoS task using the first CPU utilization with the first processing core of the CPU by selectively forcing an idle of the low QoS task during an execution window. In addition, the device executes the high QoS task using the second CPU throttling with a second processing core of the CPU.
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公开(公告)号：US10152438B2
公开(公告)日：2018-12-11
申请号：US14867770
申请日：2015-09-28
Applicant: Apple Inc.
Inventor： Derek R. Kumar , Joshua Phillips de Cesare
IPC: G06F13/24 , G06F1/32 , G06F9/4401
Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.
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5.发明申请SYSTEM AND METHOD FOR SOC IDLE POWER STATE CONTROL BASED ON I/O OPERATION CHARACTERIZATION 审中-公开基于I / O操作特性的SOC空载电源状态控制系统与方法公开(公告)号：US20160219525A1
公开(公告)日：2016-07-28
申请号：US15003551
申请日：2016-01-21
Applicant: Apple Inc.
Inventor： Derek R. Kumar
CPC classification number: H04W52/0254 , G06F1/3221 , G06F1/3243 , H04W52/0258 , Y02D10/152 , Y02D10/154 , Y02D70/142 , Y02D70/144
Abstract: A method and apparatus of a device that manages system performance by controlling power state based on information related to I/O operations is described. The device collects historical I/O information. The historical I/O information may include the number of I/O operations over a sample period of time and the inter-arrival time between I/O operations. The device further receives information related to a current I/O operation. The information of the current I/O operation may include direction, size, quality of service, and media type of the I/O operation. The device determines a power state based on the historical I/O information and the information relative to the current I/O operation to reduce power consumption while improving system efficiency and maintaining an acceptable level of system performance. The device further applies the determined power state. Other embodiments are also described and claimed.
Abstract translation: 描述了通过基于与I / O操作相关的信息控制电源状态来管理系统性能的设备的方法和装置。 设备收集历史I / O信息。 历史I / O信息可以包括在采样时间段内的I / O操作的数量和I / O操作之间的到达间隔时间。 该装置还接收与当前I / O操作有关的信息。 当前I / O操作的信息可能包括I / O操作的方向，大小，服务质量和媒体类型。 该设备基于历史I / O信息和相对于当前I / O操作的信息确定功率状态，以降低功耗，同时提高系统效率并保持可接受的系统性能水平。 该装置进一步施加确定的功率状态。 还描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US12253913B2
公开(公告)日：2025-03-18
申请号：US18438802
申请日：2024-02-12
Applicant: Apple Inc.
Inventor： Farid Nemati , Steven R. Hutsell , Derek R. Kumar , Bernard J. Semeria , James Vash , Era K. Nangia , Gregory S. Mathews
Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.
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公开(公告)号：US11934265B2
公开(公告)日：2024-03-19
申请号：US17804950
申请日：2022-06-01
Applicant: Apple Inc.
Inventor： Farid Nemati , Steven R. Hutsell , Derek R. Kumar , Bernard J. Semeria , James Vash , Era K. Nangia , Gregory S. Mathews
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/106
Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.
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公开(公告)号：US10095286B2
公开(公告)日：2018-10-09
申请号：US14503321
申请日：2014-09-30
Applicant: Apple Inc.
Inventor： Derek R. Kumar
Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device manages a thermal profile of the device by adjusting a throttling a central processing unit execution of a historically high energy consuming task. In this embodiment, the device monitors thermal level of the thermal profile of the device, the device is executing a plurality of tasks that utilize a plurality of processing cores of the device. If the thermal level of the device exceeds a thermal threshold, the device identifies one of the plurality of tasks as a historically high energy consuming task, and throttles this historically high energy consuming task by setting a force idle execution time for the historically high energy consuming task. The device further executes the plurality of tasks.
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公开(公告)号：US20170060743A1
公开(公告)日：2017-03-02
申请号：US15337526
申请日：2016-10-28
Applicant: Apple Inc.
Inventor： Derek R. Kumar
IPC: G06F12/0804 , G06F12/1045
CPC classification number: G06F12/1009 , G06F12/0804 , G06F12/1045 , G06F2212/1041 , G06F2212/455 , G06F2212/657 , G06F2212/68
Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device manages a graphics processing unit working set of pages. In this embodiment, the device determines the set of pages of the device to be analyzed, where the device includes a central processing unit and the graphics processing unit. The device additionally classifies the set of pages based on a graphics processing unit activity associated with the set of pages and evicts a page of the set of pages based on the classifying.
Abstract translation: 描述了管理图形处理单元的虚拟存储器的设备的方法和装置。 在示例性实施例中，设备管理图形处理单元工作页面集合。 在本实施例中，设备确定要分析的设备的页面集合，其中设备包括中央处理单元和图形处理单元。 该设备还基于与该组页面相关联的图形处理单元活动来对页面集进行分类，并且基于分类来逐出该页面页面。
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公开(公告)号：US09542230B2
公开(公告)日：2017-01-10
申请号：US13895262
申请日：2013-05-15
Applicant: Apple, Inc.
Inventor： Derek R. Kumar
CPC classification number: G06F9/5038 , G06F3/0614 , G06F9/4881 , Y02D10/24
Abstract: A method and apparatus of a device that coalesces the execution of several timers by scheduling the timers using a scheduling window is described. The device determines a scheduling window for each of several timers. The device selects a coalesced execution time that is within the scheduling window of the timers. The device coalesces the execution of the timers by scheduling the timers to execute at the coalesced execution time. The device can further coalesce multiple timers by opportunistic execution of the timers. In response to a detection of an opportunistic execution trigger event, the device receives multiple timers. The device selects a subset of the timers to execute based on an initial execution time and a latency time for each of the timers. The device schedules each of the subset of timers to execute during or before the opportunistic execution trigger event.
Abstract translation: 描述通过使用调度窗口调度定时器来合并多个定时器的执行的设备的方法和装置。 设备为几个定时器中的每一个确定调度窗口。 该设备选择在定时器的调度窗口内的合并执行时间。 该设备通过调度在合并执行时执行的定时器来合并定时器的执行。 该设备可以通过定时器的机会执行来进一步聚合多个定时器。 响应于机会执行触发事件的检测，该设备接收多个定时器。 设备基于每个定时器的初始执行时间和等待时间来选择要执行的定时器的子集。 该设备调度计时器的每个子集以在机会执行触发事件之前或之前执行。
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