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    INVALIDATING STORED ADDRESS TRANSLATIONS
    1.
    发明申请
    INVALIDATING STORED ADDRESS TRANSLATIONS 有权
    无效存储地址转换

    公开(公告)号：US20150242319A1

    公开(公告)日：2015-08-27

    申请号：US14186091

    申请日：2014-02-21

    Applicant: ARM LIMITED

    Inventor： Matthew L. EVANS ,  Hakan Lars-Goran PERSSON ,  Jason PARKER ,  Gareth STOCKWELL ,  Andrew Christopher ROSE

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0833 ,  G06F9/3004 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1016 ,  G06F2212/65 ,  G06F2212/683

    Abstract: A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.

    Abstract translation: 公开了一种数据处理装置和处理数据的方法，其中在第一寻址系统中使用的第一地址和第二寻址系统中使用的第二地址之间的地址转换被本地存储。 每个存储的地址转换都存储有相应的标识符。 响应于对所选存储的地址转换执行无效处理的无效命令，所选择的存储的地址转换无效，其中所选存储的地址转换在无效命令中被指定的第一地址和指定的标识符识别。 无效化处理还通过将多于一个标识符相关联的标识符分组信息进一步配置为一组标识符，并且将无效处理应用于与指定的第一地址匹配的所有存储的地址转换以及与标识符组中的任何标识符相匹配的所有存储的地址转换 指定的标识符所属的。

    SECURE INITIALISATION
    3.
    发明申请
    SECURE INITIALISATION 审中-公开

    公开(公告)号：US20180173645A1

    公开(公告)日：2018-06-21

    申请号：US15574938

    申请日：2016-04-26

    Applicant: ARM LIMITED

    Inventor： Jason PARKER ,  Richard Roy GRISENTHWAITE ,  Andrew Christopher ROSE ,  Matthew Lucien EVANS

    IPC: G06F12/14 ,  G06F12/06

    Abstract: A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.

    CACHE POWER MANAGEMENT
    5.
    发明申请
    CACHE POWER MANAGEMENT 审中-公开

    公开(公告)号：US20170255248A1

    公开(公告)日：2017-09-07

    申请号：US15447866

    申请日：2017-03-02

    Applicant: ARM Limited

    Inventor： Ashley John CRAWFORD ,  Andrew Christopher ROSE ,  Tessil THOMAS ,  David GUILLEN FANDOS

    IPC: G06F1/32

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

    COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS
    6.
    发明申请
    COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS 有权
    信息信号中断通信

    公开(公告)号：US20140122760A1

    公开(公告)日：2014-05-01

    申请号：US13661456

    申请日：2012-10-26

    Applicant: ARM LIMITED

    Inventor： Richard Roy GRISENTHWAITE ,  Anthony JEBSON ,  Andrew Christopher ROSE ,  Matthew Lucien EVANS

    IPC: G06F13/26

    CPC classification number: G06F13/26 ,  G06F13/24

    Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

    Abstract translation: 提供全局中断号码空间38用于消息信号中断。 中断目的地10,12,14,16提供有等待中断高速缓存24，其中由全局挂起状态存储器34提供的后备存储器由全部高速缓存或独立的各个未决状态存储器56共享。中断号码空间可以被划分为具有 可编程映射数据用于指示哪些中断目的地负责哪些区域。 当中断从一个中断目的地迁移到另一个中断时，这种可编程映射数据被更新。 在重新分配过程期间，待处理的中断可以被刷新回到全局挂起状态存储器34，使得该待决中断数据可以被新负责的中断目的地拾取。

    PROTECTED EXCEPTION HANDLING
    7.
    发明申请
    PROTECTED EXCEPTION HANDLING 审中-公开

    公开(公告)号：US20180150413A1

    公开(公告)日：2018-05-31

    申请号：US15578340

    申请日：2016-04-26

    Applicant: ARM LIMITED

    Inventor： Jason PARKER ,  Richard Roy GRISENTHWAITE ,  Andrew Christopher ROSE ,  Matthew Lucien EVANS

    IPC: G06F12/14 ,  G06F9/50 ,  G06F9/46 ,  G06F9/48 ,  G06F12/02 ,  G06F11/07 ,  G06F9/455

    Abstract: A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.

    SHARED PAGES
    8.
    发明申请
    SHARED PAGES 审中-公开

    公开(公告)号：US20180150251A1

    公开(公告)日：2018-05-31

    申请号：US15574549

    申请日：2016-04-26

    Applicant: ARM LIMITED

    Inventor： Jason PARKER ,  Richard Roy GRISENTHWAITE ,  Andrew Christopher ROSE

    IPC: G06F3/06 ,  G06F9/455

    Abstract: A data processing system comprising: ownership circuitry to enforce ownership rights of memory regions within a physical memory address space, a given memory region having a given owning process specified from among a plurality of processes and independently of privilege level, said given owning process having exclusive rights to control access to said given memory region, wherein said given owning process designates said given memory region as one of: private to said given owning process; and shared between said given owning process and at least one further source of memory access requests.

    ENFORCING DATA PROTECTION IN AN INTERCONNECT
    9.
    发明申请
    ENFORCING DATA PROTECTION IN AN INTERCONNECT 审中-公开
    在互连中实施数据保护

    公开(公告)号：US20160321179A1

    公开(公告)日：2016-11-03

    申请号：US14700259

    申请日：2015-04-30

    Applicant: ARM LIMITED

    Inventor： Daniel SARA ,  Antony John HARRIS ,  Håkan Lars-Göran PERSSON ,  Andrew Christopher ROSE ,  Ian BRATT

    IPC: G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0833 ,  G06F12/1491 ,  G06F2212/1052

    Abstract: Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.

    Abstract translation: 提供了互连电路和操作互连电路的方法，其中互连电路适于将至少两个主设备耦合到存储器，每个存储器包括本地高速缓存。 由互连电路介导的对存储器的访问由位于互连电路和存储器之间的存储器保护控制器来监管。 互连电路将与从主设备之一接收的存储器事务相关联的一致性类型修改为确保当由发布主设备指定的事务目标的副本的修改版本被存储在另一个的本地高速缓存中时的类型 主设备对存储器中的事务目标的访问必须发生，因此必须由存储器保护控制器进行监管。

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