公开(公告)号：US20210021544A1

公开(公告)日：2021-01-21

申请号：US16516698

申请日：2019-07-19

Applicant: Arm Limited

Inventor： Tessil THOMAS ,  Andrew Joseph RUSHING

IPC: H04L12/861

Abstract: An apparatus and method are provided for processing flush requests within a packet network. The apparatus comprises a requester device within the packet network arranged to receive a flush request generated by a remote agent requesting that one or more data items be flushed to a point of persistence. The requester device translates the flush request into a packet-based flush command conforming to a packet protocol of the packet network. A completer device within the packet network that is coupled to a persistence domain incorporating the point of persistence is arranged to detect receipt of the packet-based flush command, and then trigger a flush operation within the persistence domain to flush the one or more data items to the point of persistence. This provides a fast, hardware-based, mechanism for performing a flush operation within a persistence domain without needing to trigger software in the persistence domain to handle the flush to the point of persistence.

公开(公告)号：US20170351319A1

公开(公告)日：2017-12-07

申请号：US15173939

申请日：2016-06-06

Applicant: ARM Limited

Inventor： Dominic William BROWN ,  Ashley John CRAWFORD ,  Christopher Vincent SEVERINO ,  Tessil THOMAS

IPC: G06F1/32 ,  G06F13/24

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3206 ,  G06F13/24 ,  Y02D10/172

Abstract: An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power mode of those power modes. A system power controller controls operation of the component power control circuitry by setting a power mode lock condition therein. When the power mode lock condition is met the component power control circuitry cannot change the selected power mode of the component. Power control over the component is thus partially delegated from the system power controller to the component power control circuitry.

公开(公告)号：US20230267081A1

公开(公告)日：2023-08-24

申请号：US17678174

申请日：2022-02-23

Applicant: Arm Limited

Inventor： Jacob JOSEPH ,  Tessil THOMAS ,  Arthur Brian LAUGHTON ,  Anitha KONA ,  Jamshed JALAL

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/1045 ,  G06F12/0891

CPC classification number: G06F13/1668 ,  G06F13/161 ,  G06F12/0862 ,  G06F12/1054 ,  G06F12/1063 ,  G06F12/0891

Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.

公开(公告)号：US20180225168A1

公开(公告)日：2018-08-09

申请号：US15428550

申请日：2017-02-09

Applicant: ARM Limited

Inventor： Anitha KONA ,  Michael Wayne GARNER ,  Randall L. JONES ,  Tessil THOMAS ,  Seow Chuan LIM ,  Karthick SANTHANAM ,  Liana Christine Nicklaus

IPC: G06F11/07 ,  G06F13/24

CPC classification number: G06F11/0757 ,  G06F13/24

Abstract: A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. Interrupt receiving circuitry receives an incoming interrupt, which indicates that second processing circuitry has become unresponsive, and in response to receiving the incoming interrupt, causes the data processing apparatus to access data managed by the second processing circuitry.

公开(公告)号：US20170255248A1

公开(公告)日：2017-09-07

申请号：US15447866

申请日：2017-03-02

Applicant: ARM Limited

Inventor： Ashley John CRAWFORD ,  Andrew Christopher ROSE ,  Tessil THOMAS ,  David GUILLEN FANDOS

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/13 ,  Y02D10/14

Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

公开(公告)号：US20230140069A1

公开(公告)日：2023-05-04

申请号：US17512758

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Tessil THOMAS ,  Anitha KONA ,  Jacob JOSEPH ,  Arthur Brian LAUGHTON ,  Nandakishore SASTRY

IPC: G06F13/42

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

公开(公告)号：US20200151124A1

公开(公告)日：2020-05-14

申请号：US16186913

申请日：2018-11-12

Applicant: Arm Limited

Inventor： Tessil THOMAS

IPC: G06F13/20 ,  G06F13/42

Abstract: An apparatus and method are provided for handling address decoding in a system-on-chip (SoC). The SoC has processing circuitry for performing data processing operations, a first plurality of devices, and an interconnect to couple the processing circuitry to the first plurality of devices. The first plurality of devices are a first level of devices within a hierarchical structure of devices forming a device network. Those devices communicate using a device communication protocol which also provides an enumeration mechanism to enable software executed on the processing circuitry to discover and configure the devices within the network. The system address space provides a pool of addresses that are reserved for allocation to the first plurality of devices. An address decoder of the SoC has a device address decoder to maintain, for each device in the first plurality of devices, an indication of which addresses within the pool are allocated to that device. Hence, when a request is issued by the processing circuitry identifying an address within the pool of addresses, the device address decoder can be used to determine the appropriate device within the first plurality of devices that the request is directed to. The device address decoder is exposed to the software as a device of the device network so as to enable the software executing on the processing circuitry to discover and configure the device address decoder using the enumeration mechanism. As a result, the allocation of the pool of addresses amongst the first plurality of devices can be dynamically reconfigured under software control.

公开(公告)号：US20230176993A1

公开(公告)日：2023-06-08

申请号：US17543170

申请日：2021-12-06

Applicant: Arm Limited

Inventor： Tessil THOMAS

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F13/4221 ,  G06F12/0238 ,  G06F13/404 ,  G06F13/1673 ,  G06F13/4045

Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.

公开(公告)号：US20210240629A1

公开(公告)日：2021-08-05

申请号：US16782316

申请日：2020-02-05

Applicant: Arm Limited

Inventor： Tessil THOMAS ,  Jan-Peter LARSSON

IPC: G06F12/0891 ,  G06F12/0882 ,  G06F12/109 ,  G06F7/58 ,  G06F12/1027 ,  G06F11/07 ,  H04L9/08 ,  G06F12/1081 ,  G06F11/30 ,  G06F12/0873 ,  H04L9/06 ,  H04L9/32

Abstract: An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.

公开(公告)号：US20200042463A1

公开(公告)日：2020-02-06

申请号：US16053899

申请日：2018-08-03

Applicant: Arm Limited

Inventor： Tessil THOMAS ,  Jamshed JALAL ,  Andrea PELLEGRINI ,  Anitha KONA

IPC: G06F12/14 ,  G06F13/42 ,  G06F12/1081

Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.